From patchwork Tue Oct 3 07:06:06 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 9981819 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2744860365 for ; Tue, 3 Oct 2017 07:06:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1A36D28877 for ; Tue, 3 Oct 2017 07:06:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0ED872887B; Tue, 3 Oct 2017 07:06:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B502728877 for ; Tue, 3 Oct 2017 07:06:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4114A6E3CD; Tue, 3 Oct 2017 07:06:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 442106E3C9 for ; Tue, 3 Oct 2017 07:06:26 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga102.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 03 Oct 2017 00:06:24 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,473,1500966000"; d="scan'208";a="906141478" Received: from mrsarkar-mobl2.amr.corp.intel.com (HELO rdvivi-vienna.intel.com) ([10.252.138.57]) by FMSMGA003.fm.intel.com with ESMTP; 03 Oct 2017 00:06:24 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Oct 2017 00:06:06 -0700 Message-Id: <20171003070614.18396-6-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171003070614.18396-1-rodrigo.vivi@intel.com> References: <20171003070614.18396-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Cc: Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH 05/13] drm/i915/cnl: extract cnl_dvfs_{pre, post}_change X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Paulo Zanoni These functions even have their own page in our spec, so extract them from cnl_set_cdclk(). v2: (By Rodrigo) Fixed inverted logic on error return of cnl_dvfs_pre_change. Cc: Ville Syrjälä Signed-off-by: Paulo Zanoni Signed-off-by: Rodrigo Vivi Reviewed-by: James Ausmus Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/intel_cdclk.c | 33 +++++++++++++++++++++++---------- 1 file changed, 23 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 87fc42b19336..b35eb145d66e 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1510,12 +1510,8 @@ static void cnl_cdclk_pll_enable(struct drm_i915_private *dev_priv, int vco) dev_priv->cdclk.hw.vco = vco; } -static void cnl_set_cdclk(struct drm_i915_private *dev_priv, - const struct intel_cdclk_state *cdclk_state) +static int cnl_dvfs_pre_change(struct drm_i915_private *dev_priv) { - int cdclk = cdclk_state->cdclk; - int vco = cdclk_state->vco; - u32 val, divider, pcu_ack; int ret; mutex_lock(&dev_priv->rps.hw_lock); @@ -1524,11 +1520,30 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv, SKL_CDCLK_READY_FOR_CHANGE, SKL_CDCLK_READY_FOR_CHANGE, 3); mutex_unlock(&dev_priv->rps.hw_lock); - if (ret) { + + if (ret) DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n", ret); + + return ret; +} + +static void cnl_dvfs_post_change(struct drm_i915_private *dev_priv, int level) +{ + mutex_lock(&dev_priv->rps.hw_lock); + sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, level); + mutex_unlock(&dev_priv->rps.hw_lock); +} + +static void cnl_set_cdclk(struct drm_i915_private *dev_priv, + const struct intel_cdclk_state *cdclk_state) +{ + int cdclk = cdclk_state->cdclk; + int vco = cdclk_state->vco; + u32 val, divider, pcu_ack; + + if (cnl_dvfs_pre_change(dev_priv)) return; - } /* cdclk = vco / 2 / div{1,2} */ switch (DIV_ROUND_CLOSEST(vco, cdclk)) { @@ -1575,9 +1590,7 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv, I915_WRITE(CDCLK_CTL, val); /* inform PCU of the change */ - mutex_lock(&dev_priv->rps.hw_lock); - sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL, pcu_ack); - mutex_unlock(&dev_priv->rps.hw_lock); + cnl_dvfs_post_change(dev_priv, pcu_ack); intel_update_cdclk(dev_priv); }