From patchwork Tue Oct 3 07:06:08 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 9981817 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4F08A60365 for ; Tue, 3 Oct 2017 07:06:30 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 41C4028877 for ; Tue, 3 Oct 2017 07:06:30 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 36A602887B; Tue, 3 Oct 2017 07:06:30 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id D4D9928877 for ; Tue, 3 Oct 2017 07:06:29 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3327F6E3CB; Tue, 3 Oct 2017 07:06:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id 49EE46E3CB for ; Tue, 3 Oct 2017 07:06:26 +0000 (UTC) Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga104.jf.intel.com with ESMTP; 03 Oct 2017 00:06:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.42,473,1500966000"; d="scan'208";a="906141489" Received: from mrsarkar-mobl2.amr.corp.intel.com (HELO rdvivi-vienna.intel.com) ([10.252.138.57]) by FMSMGA003.fm.intel.com with ESMTP; 03 Oct 2017 00:06:25 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 3 Oct 2017 00:06:08 -0700 Message-Id: <20171003070614.18396-8-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20171003070614.18396-1-rodrigo.vivi@intel.com> References: <20171003070614.18396-1-rodrigo.vivi@intel.com> MIME-Version: 1.0 Cc: Kahola@freedesktop.org, Paulo Zanoni , Rodrigo Vivi Subject: [Intel-gfx] [PATCH 07/13] drm/i915/cnl: DVFS for PLL enabling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: "Kahola, Mika" Display Voltage and Frequency Switching (DVFS) is used to adjust the display voltage to match the display clock frequencies. If voltage is set too low, it will break functionality. If voltage is set too high, it will waste power. Voltage level is selected based on CD clock and DDI clock. The sequence before frequency change is the following and it requests the power controller to raise voltage to maximum - Ensure any previous GT Driver Mailbox transaction is complete. - Write GT Driver Mailbox Data Low = 0x3. - Write GT Driver Mailbox Data High = 0x0. - Write GT Driver Mailbox Interface = 0x80000007. - Poll GT Driver Mailbox Interface for Run/Busy indication cleared (bit 31 = 0). - Read GT Driver Mailbox Data Low, if bit 0 is 0x1, continue, else restart the sequence. Timeout after 3ms The sequence after frequency change is the following and it requests the port controller to raise voltage to the requested level. - Write GT Driver Mailbox Data Low * For level 0, write 0x0 * For level 1, write 0x1 * For level 2, write 0x2 * For level 3, write 0x3 - Write GT Driver Mailbox Data High = 0x0. - Write GT Driver Mailbox Interface = 0x80000007. For Cannonlake, the level 3 is not used and it aliases to level 2. v2: reuse Paulo's work on cdclk. This patch depends on Paulo's patch [PATCH 02/12] drm/i915/cnl: extract cnl_dvfs_{pre,post}_change v3: (By Rodrigo): Remove duplicated commend and fix typo on Paulo's name. v4: (By Rodrigo): Rebase on top "Unify and export gen9+ port_clock calculation" The port clock calculation here was only addressing DP, so let's reuse the current port calculation that is already in place without any duplication. Alos fix portclk <= 594000 instead of portclk < 594000. Cc: Paulo Zanoni Cc: Ville Syrjälä Signed-off-by: Kahola, Mika Signed-off-by: Rodrigo Vivi Reviewed-by: Manasi Navare --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 30 ++++++++++++++++++++++-------- 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index a2a3d93d67bd..6030fbafa580 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -1966,10 +1966,23 @@ static const struct intel_dpll_mgr bxt_pll_mgr = { .dump_hw_state = bxt_dump_hw_state, }; +static int cnl_get_dvfs_level(int cdclk, int portclk) +{ + if (cdclk == 168000 && portclk <= 594000) + return 0; + else if (cdclk == 336000 && portclk <= 594000) + return 1; + else + return 2; +} + static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, struct intel_shared_dpll *pll) { uint32_t val; + int ret; + int level; + int cdclk, portclk; /* 1. Enable DPLL power in DPLL_ENABLE. */ val = I915_READ(CNL_DPLL_ENABLE(pll->id)); @@ -2006,11 +2019,9 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, /* * 5. If the frequency will result in a change to the voltage * requirement, follow the Display Voltage Frequency Switching - * Sequence Before Frequency Change - * - * FIXME: (DVFS) is used to adjust the display voltage to match the - * display clock frequencies + * (DVFS) Sequence Before Frequency Change */ + ret = cnl_dvfs_pre_change(dev_priv); /* 6. Enable DPLL in DPLL_ENABLE. */ val = I915_READ(CNL_DPLL_ENABLE(pll->id)); @@ -2028,11 +2039,14 @@ static void cnl_ddi_pll_enable(struct drm_i915_private *dev_priv, /* * 8. If the frequency will result in a change to the voltage * requirement, follow the Display Voltage Frequency Switching - * Sequence After Frequency Change - * - * FIXME: (DVFS) is used to adjust the display voltage to match the - * display clock frequencies + * (DVFS) Sequence After Frequency Change */ + if (ret == 0) { + cdclk = dev_priv->cdclk.hw.cdclk; + portclk = intel_ddi_port_clock(dev_priv, pll->id); + level = cnl_get_dvfs_level(cdclk, portclk); + cnl_dvfs_post_change(dev_priv, level); + } /* * 9. turn on the clock for the DDI and map the DPLL to the DDI