| Message ID | 20171003223142.26264-1-rodrigo.vivi@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Em Ter, 2017-10-03 às 15:31 -0700, Rodrigo Vivi escreveu: > This is heavily based on a initial patch provided by Ville > plus all changes provided later by Ander. > > As Geminilake, Cannonlake also supports 2 pixels per clock. > > Different from Geminilake we are not implementing the 99% Wa. > But we can revisit that decision later if we find out > any limitation on later CNL SKUs. > > v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track > minimum acceptable cdclk instead of "minimum dotclock")' > > v3: When fixing HDMI on CNL I noticed that I missed to convert > back the doubled pixel rate to cdclk. > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Jani Nikula <jani.nikula@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_cdclk.c | 14 ++------------ > drivers/gpu/drm/i915/intel_display.c | 2 +- > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > 3 files changed, 5 insertions(+), 14 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > b/drivers/gpu/drm/i915/intel_cdclk.c > index 58ee4dd07cf6..bdb95b75c9d4 100644 > --- a/drivers/gpu/drm/i915/intel_cdclk.c > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > @@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct > drm_i915_private *dev_priv, > int pixel_rate) > { > if (INTEL_GEN(dev_priv) >= 10) > - /* > - * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2) > - * once DDI clock voltage requirements are > - * handled correctly. > - */ > - return pixel_rate; > + return DIV_ROUND_UP(pixel_rate, 2); > else if (IS_GEMINILAKE(dev_priv)) > /* > * FIXME: Avoid using a pixel clock that is more > than 99% of the cdclk > @@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct > drm_i915_private *dev_priv) > int max_cdclk_freq = dev_priv->max_cdclk_freq; > > if (INTEL_GEN(dev_priv) >= 10) > - /* > - * FIXME: Allow '2 * max_cdclk_freq' > - * once DDI clock voltage requirements are > - * handled correctly. > - */ > - return max_cdclk_freq; > + return 2 * max_cdclk_freq; > else if (IS_GEMINILAKE(dev_priv)) > /* > * FIXME: Limiting to 99% as a temporary workaround. > See > diff --git a/drivers/gpu/drm/i915/intel_display.c > b/drivers/gpu/drm/i915/intel_display.c > index b7a6ddc6a66d..644759aff069 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, > struct intel_crtc_state *crtc_state > crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; > max_dotclk = to_intel_atomic_state(crtc_state->base.state)- > >cdclk.logical.cdclk; > > - if (IS_GEMINILAKE(dev_priv)) > + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) > max_dotclk *= 2; > > if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) > diff --git a/drivers/gpu/drm/i915/intel_pm.c > b/drivers/gpu/drm/i915/intel_pm.c > index 171b21f6c4ad..ede871b7982e 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct > intel_crtc_state *crtc_state) > int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, > struct intel_crtc_state *cstate) > { > + struct drm_i915_private *dev_priv = to_i915(intel_crtc- > >base.dev); > struct drm_crtc_state *crtc_state = &cstate->base; > struct drm_atomic_state *state = crtc_state->state; > struct drm_plane *plane; > @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct > intel_crtc *intel_crtc, > crtc_clock = crtc_state->adjusted_mode.crtc_clock; > dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; > > - if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev))) > + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) > dotclk *= 2; > > pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, > pipe_downscale);
On Wed, Oct 04, 2017 at 11:28:26PM +0000, Paulo Zanoni wrote: > Em Ter, 2017-10-03 às 15:31 -0700, Rodrigo Vivi escreveu: > > This is heavily based on a initial patch provided by Ville > > plus all changes provided later by Ander. > > > > As Geminilake, Cannonlake also supports 2 pixels per clock. > > > > Different from Geminilake we are not implementing the 99% Wa. > > But we can revisit that decision later if we find out > > any limitation on later CNL SKUs. > > > > v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track > > minimum acceptable cdclk instead of "minimum dotclock")' > > > > v3: When fixing HDMI on CNL I noticed that I missed to convert > > back the doubled pixel rate to cdclk. > > > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> I just merged to dinq now that dvfs also got merged. Thanks for reviwing. > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> > > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: Jani Nikula <jani.nikula@intel.com> > > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > --- > > drivers/gpu/drm/i915/intel_cdclk.c | 14 ++------------ > > drivers/gpu/drm/i915/intel_display.c | 2 +- > > drivers/gpu/drm/i915/intel_pm.c | 3 ++- > > 3 files changed, 5 insertions(+), 14 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_cdclk.c > > b/drivers/gpu/drm/i915/intel_cdclk.c > > index 58ee4dd07cf6..bdb95b75c9d4 100644 > > --- a/drivers/gpu/drm/i915/intel_cdclk.c > > +++ b/drivers/gpu/drm/i915/intel_cdclk.c > > @@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct > > drm_i915_private *dev_priv, > > int pixel_rate) > > { > > if (INTEL_GEN(dev_priv) >= 10) > > - /* > > - * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2) > > - * once DDI clock voltage requirements are > > - * handled correctly. > > - */ > > - return pixel_rate; > > + return DIV_ROUND_UP(pixel_rate, 2); > > else if (IS_GEMINILAKE(dev_priv)) > > /* > > * FIXME: Avoid using a pixel clock that is more > > than 99% of the cdclk > > @@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct > > drm_i915_private *dev_priv) > > int max_cdclk_freq = dev_priv->max_cdclk_freq; > > > > if (INTEL_GEN(dev_priv) >= 10) > > - /* > > - * FIXME: Allow '2 * max_cdclk_freq' > > - * once DDI clock voltage requirements are > > - * handled correctly. > > - */ > > - return max_cdclk_freq; > > + return 2 * max_cdclk_freq; > > else if (IS_GEMINILAKE(dev_priv)) > > /* > > * FIXME: Limiting to 99% as a temporary workaround. > > See > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index b7a6ddc6a66d..644759aff069 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, > > struct intel_crtc_state *crtc_state > > crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; > > max_dotclk = to_intel_atomic_state(crtc_state->base.state)- > > >cdclk.logical.cdclk; > > > > - if (IS_GEMINILAKE(dev_priv)) > > + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) > > max_dotclk *= 2; > > > > if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c > > b/drivers/gpu/drm/i915/intel_pm.c > > index 171b21f6c4ad..ede871b7982e 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct > > intel_crtc_state *crtc_state) > > int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, > > struct intel_crtc_state *cstate) > > { > > + struct drm_i915_private *dev_priv = to_i915(intel_crtc- > > >base.dev); > > struct drm_crtc_state *crtc_state = &cstate->base; > > struct drm_atomic_state *state = crtc_state->state; > > struct drm_plane *plane; > > @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct > > intel_crtc *intel_crtc, > > crtc_clock = crtc_state->adjusted_mode.crtc_clock; > > dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; > > > > - if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev))) > > + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) > > dotclk *= 2; > > > > pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, > > pipe_downscale); > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index 58ee4dd07cf6..bdb95b75c9d4 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -1793,12 +1793,7 @@ static int intel_pixel_rate_to_cdclk(struct drm_i915_private *dev_priv, int pixel_rate) { if (INTEL_GEN(dev_priv) >= 10) - /* - * FIXME: Switch to DIV_ROUND_UP(pixel_rate, 2) - * once DDI clock voltage requirements are - * handled correctly. - */ - return pixel_rate; + return DIV_ROUND_UP(pixel_rate, 2); else if (IS_GEMINILAKE(dev_priv)) /* * FIXME: Avoid using a pixel clock that is more than 99% of the cdclk @@ -2057,12 +2052,7 @@ static int intel_compute_max_dotclk(struct drm_i915_private *dev_priv) int max_cdclk_freq = dev_priv->max_cdclk_freq; if (INTEL_GEN(dev_priv) >= 10) - /* - * FIXME: Allow '2 * max_cdclk_freq' - * once DDI clock voltage requirements are - * handled correctly. - */ - return max_cdclk_freq; + return 2 * max_cdclk_freq; else if (IS_GEMINILAKE(dev_priv)) /* * FIXME: Limiting to 99% as a temporary workaround. See diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b7a6ddc6a66d..644759aff069 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12827,7 +12827,7 @@ skl_max_scale(struct intel_crtc *intel_crtc, struct intel_crtc_state *crtc_state crtc_clock = crtc_state->base.adjusted_mode.crtc_clock; max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk; - if (IS_GEMINILAKE(dev_priv)) + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) max_dotclk *= 2; if (WARN_ON_ONCE(!crtc_clock || max_dotclk < crtc_clock)) diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 171b21f6c4ad..ede871b7982e 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -3932,6 +3932,7 @@ skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state) int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, struct intel_crtc_state *cstate) { + struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); struct drm_crtc_state *crtc_state = &cstate->base; struct drm_atomic_state *state = crtc_state->state; struct drm_plane *plane; @@ -3974,7 +3975,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, crtc_clock = crtc_state->adjusted_mode.crtc_clock; dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; - if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev))) + if (IS_GEMINILAKE(dev_priv) || INTEL_GEN(dev_priv) >= 10) dotclk *= 2; pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale);
This is heavily based on a initial patch provided by Ville plus all changes provided later by Ander. As Geminilake, Cannonlake also supports 2 pixels per clock. Different from Geminilake we are not implementing the 99% Wa. But we can revisit that decision later if we find out any limitation on later CNL SKUs. v2: Rebase on top of commit 'd305e0614601 ("drm/i915: Track minimum acceptable cdclk instead of "minimum dotclock")' v3: When fixing HDMI on CNL I noticed that I missed to convert back the doubled pixel rate to cdclk. Cc: Paulo Zanoni <paulo.r.zanoni@intel.com> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Jani Nikula <jani.nikula@intel.com> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/intel_cdclk.c | 14 ++------------ drivers/gpu/drm/i915/intel_display.c | 2 +- drivers/gpu/drm/i915/intel_pm.c | 3 ++- 3 files changed, 5 insertions(+), 14 deletions(-)