From patchwork Tue Oct 17 17:38:19 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 10012621 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AD60660211 for ; Tue, 17 Oct 2017 17:38:26 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9A749289B2 for ; Tue, 17 Oct 2017 17:38:26 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8F18E289B4; Tue, 17 Oct 2017 17:38:26 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E2D4D289B2 for ; Tue, 17 Oct 2017 17:38:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B2E7A6E706; Tue, 17 Oct 2017 17:38:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id BEAC46E705 for ; Tue, 17 Oct 2017 17:38:22 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by orsmga105.jf.intel.com with ESMTP; 17 Oct 2017 10:38:22 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.43,391,1503385200"; d="scan'208";a="139345693" Received: from rdvivi-vienna.jf.intel.com ([10.7.196.88]) by orsmga004.jf.intel.com with ESMTP; 17 Oct 2017 10:38:22 -0700 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 17 Oct 2017 10:38:19 -0700 Message-Id: <20171017173819.8054-1-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.13.5 MIME-Version: 1.0 Cc: Arthur J Runyan , Rodrigo Vivi Subject: [Intel-gfx] [PATCH] drm/i915: Apply Wa Display #1183 on skl, kbl, and cfl. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Wa Display #1183 was recently added to workaround "Failures when enabling DPLL0 with eDP link rate 2.16 or 4.32 GHz and CD clock frequency 308.57 or 617.14 MHz (CDCLK_CTL CD Frequency Select 10b or 11b) used in this enabling or in previous enabling." However our code is already not following the "Skylake Seqyences to Initialize Display" line by line so it was really hard to map this workaround there. The biggest difference is that Spec sequence expect that by the time we are enabling DPLL0 we already know the eDP link rate. What it is not true for us. We handle eDP link rate as any other DP link rate at the modeset. With only one small difference that we check a VCO when that is available. WARN: It seems that DPLL0 link rate was not designed to change on the fly and we will probably need to find a more robuts solution caching the eDP link rate somehow. This Workaround was designed to minimize the impact only to save the bad case with that link rates. But HW engineers indicated that it should be safe to apply broadly. Although they were expecting the DPLL0 link rate to be unchanged on runtime. Cc: Arthur J Runyan Cc: Ville Syrjälä Signed-off-by: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_reg.h | 2 ++ drivers/gpu/drm/i915/intel_cdclk.c | 33 +++++++++++++++++++++++++++------ drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++++++ 3 files changed, 39 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5f99d4d6291b..446f4b6fade1 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -6980,6 +6980,7 @@ enum { #define RESET_PCH_HANDSHAKE_ENABLE (1<<4) #define GEN8_CHICKEN_DCPR_1 _MMIO(0x46430) +#define SKL_SELECT_ALTERNATE_DC_EXIT (1<<30) #define MASK_WAKEMEM (1<<13) #define SKL_DFSM _MMIO(0x51000) @@ -8525,6 +8526,7 @@ enum skl_power_gate { #define BXT_CDCLK_CD2X_DIV_SEL_4 (3<<22) #define BXT_CDCLK_CD2X_PIPE(pipe) ((pipe)<<20) #define BXT_CDCLK_CD2X_PIPE_NONE BXT_CDCLK_CD2X_PIPE(3) +#define DIVMUX_CD_OVERRIDE (1<<19) #define BXT_CDCLK_SSA_PRECHARGE_ENABLE (1<<16) #define CDCLK_FREQ_DECIMAL_MASK (0x7ff) diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c index b2a6d62b71c0..e193912b21ec 100644 --- a/drivers/gpu/drm/i915/intel_cdclk.c +++ b/drivers/gpu/drm/i915/intel_cdclk.c @@ -858,7 +858,8 @@ static void skl_set_preferred_cdclk_vco(struct drm_i915_private *dev_priv, intel_update_max_cdclk(dev_priv); } -static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) +static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco, + u32 freq_select) { int min_cdclk = skl_calc_cdclk(0, vco); u32 val; @@ -894,6 +895,11 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) I915_WRITE(DPLL_CTRL1, val); POSTING_READ(DPLL_CTRL1); + /* Wa Display #1183: skl,kbl,cfl */ + val = I915_READ(CDCLK_CTL); + val |= DIVMUX_CD_OVERRIDE; + I915_WRITE(CDCLK_CTL, val); + I915_WRITE(LCPLL1_CTL, I915_READ(LCPLL1_CTL) | LCPLL_PLL_ENABLE); if (intel_wait_for_register(dev_priv, @@ -901,6 +907,18 @@ static void skl_dpll0_enable(struct drm_i915_private *dev_priv, int vco) 5)) DRM_ERROR("DPLL0 not locked\n"); + /* Wa Display #1183: skl,kbl,cfl */ + val = I915_READ(CDCLK_CTL); + val &= ~CDCLK_FREQ_SEL_MASK;; + I915_WRITE(CDCLK_CTL, val); + + I915_WRITE(CDCLK_CTL, freq_select); + POSTING_READ(CDCLK_CTL); + + val = I915_READ(CDCLK_CTL); + val &= ~DIVMUX_CD_OVERRIDE; + I915_WRITE(CDCLK_CTL, val); + dev_priv->cdclk.hw.vco = vco; /* We'll want to keep using the current vco from now on. */ @@ -964,15 +982,18 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv, break; } + freq_select |= skl_cdclk_decimal(cdclk); + if (dev_priv->cdclk.hw.vco != 0 && dev_priv->cdclk.hw.vco != vco) skl_dpll0_disable(dev_priv); - if (dev_priv->cdclk.hw.vco != vco) - skl_dpll0_enable(dev_priv, vco); - - I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(cdclk)); - POSTING_READ(CDCLK_CTL); + if (dev_priv->cdclk.hw.vco != vco) { + skl_dpll0_enable(dev_priv, vco, freq_select); + } else { + I915_WRITE(CDCLK_CTL, freq_select); + POSTING_READ(CDCLK_CTL); + } /* inform PCU of the change */ mutex_lock(&dev_priv->pcu_lock); diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c index 8af286c63d3b..e0bc2debdad0 100644 --- a/drivers/gpu/drm/i915/intel_runtime_pm.c +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c @@ -598,6 +598,11 @@ void gen9_enable_dc5(struct drm_i915_private *dev_priv) DRM_DEBUG_KMS("Enabling DC5\n"); + /* Wa Display #1183: skl,kbl,cfl */ + if (IS_GEN9_BC(dev_priv)) + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | + SKL_SELECT_ALTERNATE_DC_EXIT); + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5); } @@ -625,6 +630,11 @@ void skl_disable_dc6(struct drm_i915_private *dev_priv) { DRM_DEBUG_KMS("Disabling DC6\n"); + /* Wa Display #1183: skl,kbl,cfl */ + if (IS_GEN9_BC(dev_priv)) + I915_WRITE(GEN8_CHICKEN_DCPR_1, I915_READ(GEN8_CHICKEN_DCPR_1) | + SKL_SELECT_ALTERNATE_DC_EXIT); + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE); }