| Message ID | 20171027094523.9317-1-ville.syrjala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 27 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > DP dongles may signal downstream HPD via short HPD pulses. Setting the > sink to DPMS off apparently kills the downstream HPD (at least on my > DP->VGA dongle), so skip the DPMS off for such dongles when we turn > off the port. > > v2: Deal with DDI as well by moving the check into > intel_dp_sink_dpms() (Dhinakaran) > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: David Woodhouse <dwmw2@infradead.org> > Cc: Imre Deak <imre.deak@intel.com> > Cc: Pablo <pablodebiase@nanalysis.com> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103472 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99114 > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++++++ > 1 file changed, 18 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index aa75f55eeb61..59169a4dc9d3 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -2505,6 +2505,21 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp) > udelay(200); > } > > +static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) > +{ > + /* > + * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus > + * be capable of signalling downstream hpd with a long pulse. > + * Whether or not that means D3 is safe to use is not clear, > + * but let's assume so until proven otherwise. > + * > + * FIXME should really check all downstream ports... > + */ > + return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && > + intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && > + intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; > +} > + > /* If the sink supports it, try to set the power state appropriately */ > void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) > { > @@ -2515,6 +2530,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) > return; > > if (mode != DRM_MODE_DPMS_ON) { > + if (downstream_hpd_needs_d0(intel_dp)) > + return; > + > ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > DP_SET_POWER_D3); > } else {
On Fri, Oct 27, 2017 at 01:02:24PM +0300, Jani Nikula wrote: > On Fri, 27 Oct 2017, Ville Syrjala <ville.syrjala@linux.intel.com> wrote: > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > DP dongles may signal downstream HPD via short HPD pulses. Setting the > > sink to DPMS off apparently kills the downstream HPD (at least on my > > DP->VGA dongle), so skip the DPMS off for such dongles when we turn > > off the port. > > > > v2: Deal with DDI as well by moving the check into > > intel_dp_sink_dpms() (Dhinakaran) > > > > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > > Cc: David Woodhouse <dwmw2@infradead.org> > > Cc: Imre Deak <imre.deak@intel.com> > > Cc: Pablo <pablodebiase@nanalysis.com> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103472 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99114 > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Reviewed-by: Jani Nikula <jani.nikula@intel.com> Thanks for the review. Patch pushed to dinq. > > > > --- > > drivers/gpu/drm/i915/intel_dp.c | 18 ++++++++++++++++++ > > 1 file changed, 18 insertions(+) > > > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > > index aa75f55eeb61..59169a4dc9d3 100644 > > --- a/drivers/gpu/drm/i915/intel_dp.c > > +++ b/drivers/gpu/drm/i915/intel_dp.c > > @@ -2505,6 +2505,21 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp) > > udelay(200); > > } > > > > +static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) > > +{ > > + /* > > + * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus > > + * be capable of signalling downstream hpd with a long pulse. > > + * Whether or not that means D3 is safe to use is not clear, > > + * but let's assume so until proven otherwise. > > + * > > + * FIXME should really check all downstream ports... > > + */ > > + return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && > > + intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && > > + intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; > > +} > > + > > /* If the sink supports it, try to set the power state appropriately */ > > void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) > > { > > @@ -2515,6 +2530,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) > > return; > > > > if (mode != DRM_MODE_DPMS_ON) { > > + if (downstream_hpd_needs_d0(intel_dp)) > > + return; > > + > > ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, > > DP_SET_POWER_D3); > > } else { > > -- > Jani Nikula, Intel Open Source Technology Center
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index aa75f55eeb61..59169a4dc9d3 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -2505,6 +2505,21 @@ static void ironlake_edp_pll_off(struct intel_dp *intel_dp) udelay(200); } +static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) +{ + /* + * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus + * be capable of signalling downstream hpd with a long pulse. + * Whether or not that means D3 is safe to use is not clear, + * but let's assume so until proven otherwise. + * + * FIXME should really check all downstream ports... + */ + return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && + intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && + intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; +} + /* If the sink supports it, try to set the power state appropriately */ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) { @@ -2515,6 +2530,9 @@ void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) return; if (mode != DRM_MODE_DPMS_ON) { + if (downstream_hpd_needs_d0(intel_dp)) + return; + ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D3); } else {