diff mbox

[v2] drm/i915: Implement ReadHitWriteOnlyDisable.

Message ID 20171103183027.5051-1-rafael.antognolli@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Rafael Antognolli Nov. 3, 2017, 6:30 p.m. UTC 
The workaround for this is described as:

"if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"

Further documentation in the internal bug referenced by the bspec
suggest that any of the above suggestions should suffice to fix the
issue. We are going with disabling RCC clock gating.

Unfortunately, what we are doing doesn't match the name of the
workaround, but at least it matches its description.

This change improves CNL stability by avoiding some of the hangs seen in
the platform.

v2: Only disable RCC clock gating.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h        | 1 +
 drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
 2 files changed, 4 insertions(+)

Comments

Rodrigo Vivi Nov. 8, 2017, 8:07 p.m. UTC | #1 
On Fri, Nov 03, 2017 at 06:30:27PM +0000, Rafael Antognolli wrote:
> The workaround for this is described as:
> 
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
> 
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
> 
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
> 
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
> 
> v2: Only disable RCC clock gating.
> 
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
>   */
>  #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
>  #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
> +#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
>  
>  /*
>   * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>  			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>  
> +	/* ReadHitWriteOnlyDisable: cnl */
> +	WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> +
>  	/* WaEnablePreemptionGranularityControlByUMD:cnl */
>  	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
>  		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Rodrigo Vivi Nov. 8, 2017, 8:47 p.m. UTC | #2 
On Fri, Nov 03, 2017 at 06:30:27PM +0000, Rafael Antognolli wrote:
> The workaround for this is described as:
> 
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
> 
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
> 
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
> 
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
> 
> v2: Only disable RCC clock gating.
> 
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>

Merged to dinq. Thanks for the patch.

> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
>   */
>  #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
>  #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
> +#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
>  
>  /*
>   * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>  	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>  			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>  
> +	/* ReadHitWriteOnlyDisable: cnl */
> +	WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> +
>  	/* WaEnablePreemptionGranularityControlByUMD:cnl */
>  	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
>  		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));
> -- 
> 2.13.6
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Chris Wilson Nov. 10, 2017, 9:21 p.m. UTC | #3 
Quoting Rafael Antognolli (2017-11-03 18:30:27)
> The workaround for this is described as:
> 
> "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
> 
> Further documentation in the internal bug referenced by the bspec
> suggest that any of the above suggestions should suffice to fix the
> issue. We are going with disabling RCC clock gating.
> 
> Unfortunately, what we are doing doesn't match the name of the
> workaround, but at least it matches its description.
> 
> This change improves CNL stability by avoiding some of the hangs seen in
> the platform.
> 
> v2: Only disable RCC clock gating.
> 
> Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h        | 1 +
>  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
>  2 files changed, 4 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8c775e96b4e4..bd36ec9bc93f 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3837,6 +3837,7 @@ enum {
>   */
>  #define SLICE_UNIT_LEVEL_CLKGATE       _MMIO(0x94d4)
>  #define  SARBUNIT_CLKGATE_DIS          (1 << 5)
> +#define  RCCUNIT_CLKGATE_DIS           (1 << 7)
>  
>  /*
>   * Display engine regs
> diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> index f31f2d6384c3..3af0dcb91e9c 100644
> --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
>         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
>                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
>  
> +       /* ReadHitWriteOnlyDisable: cnl */
> +       WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);

This is not sticking. Why are we applying SLICE_UNIT_LEVEL_CLKGATE as a
context register here, and as an ordinary unmasked register over in
cnl_init_clock_gating() ?
-Chris
Rafael Antognolli Nov. 10, 2017, 10:01 p.m. UTC | #4 
On Fri, Nov 10, 2017 at 09:21:51PM +0000, Chris Wilson wrote:
> Quoting Rafael Antognolli (2017-11-03 18:30:27)
> > The workaround for this is described as:
> > 
> > "if RenderSurfaceState.Num_Multisamples > 1, disable RCC clock gating if
> > RenderSurfaceState.Num_Multisamples == 1, set 0x7010[14] = 1"
> > 
> > Further documentation in the internal bug referenced by the bspec
> > suggest that any of the above suggestions should suffice to fix the
> > issue. We are going with disabling RCC clock gating.
> > 
> > Unfortunately, what we are doing doesn't match the name of the
> > workaround, but at least it matches its description.
> > 
> > This change improves CNL stability by avoiding some of the hangs seen in
> > the platform.
> > 
> > v2: Only disable RCC clock gating.
> > 
> > Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h        | 1 +
> >  drivers/gpu/drm/i915/intel_engine_cs.c | 3 +++
> >  2 files changed, 4 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 8c775e96b4e4..bd36ec9bc93f 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3837,6 +3837,7 @@ enum {
> >   */
> >  #define SLICE_UNIT_LEVEL_CLKGATE       _MMIO(0x94d4)
> >  #define  SARBUNIT_CLKGATE_DIS          (1 << 5)
> > +#define  RCCUNIT_CLKGATE_DIS           (1 << 7)
> >  
> >  /*
> >   * Display engine regs
> > diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
> > index f31f2d6384c3..3af0dcb91e9c 100644
> > --- a/drivers/gpu/drm/i915/intel_engine_cs.c
> > +++ b/drivers/gpu/drm/i915/intel_engine_cs.c
> > @@ -1320,6 +1320,9 @@ static int cnl_init_workarounds(struct intel_engine_cs *engine)
> >         WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
> >                             GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
> >  
> > +       /* ReadHitWriteOnlyDisable: cnl */
> > +       WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
> 
> This is not sticking. Why are we applying SLICE_UNIT_LEVEL_CLKGATE as a
> context register here, and as an ordinary unmasked register over in
> cnl_init_clock_gating() ?

Ugh, I didn't know there was a better place for this. Feel free to move it to
cnl_init_clock_gating(), or I can send a patch soon. Sorry for the mess.

Rafael
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 8c775e96b4e4..bd36ec9bc93f 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3837,6 +3837,7 @@  enum {
  */
 #define SLICE_UNIT_LEVEL_CLKGATE	_MMIO(0x94d4)
 #define  SARBUNIT_CLKGATE_DIS		(1 << 5)
+#define  RCCUNIT_CLKGATE_DIS		(1 << 7)
 
 /*
  * Display engine regs
diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index f31f2d6384c3..3af0dcb91e9c 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -1320,6 +1320,9 @@  static int cnl_init_workarounds(struct intel_engine_cs *engine)
 	WA_SET_FIELD_MASKED(GEN8_CS_CHICKEN1, GEN9_PREEMPT_GPGPU_LEVEL_MASK,
 			    GEN9_PREEMPT_GPGPU_COMMAND_LEVEL);
 
+	/* ReadHitWriteOnlyDisable: cnl */
+	WA_SET_BIT_MASKED(SLICE_UNIT_LEVEL_CLKGATE, RCCUNIT_CLKGATE_DIS);
+
 	/* WaEnablePreemptionGranularityControlByUMD:cnl */
 	I915_WRITE(GEN7_FF_SLICE_CS_CHICKEN1,
 		   _MASKED_BIT_ENABLE(GEN9_FFSC_PERCTX_PREEMPT_CTRL));