From patchwork Thu Nov 9 18:51:01 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hans de Goede X-Patchwork-Id: 10051695 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 558AE60631 for ; Thu, 9 Nov 2017 18:51:12 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 488A52B06E for ; Thu, 9 Nov 2017 18:51:12 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3D16C2B072; Thu, 9 Nov 2017 18:51:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B2B5D2B06E for ; Thu, 9 Nov 2017 18:51:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 9B28C6E107; Thu, 9 Nov 2017 18:51:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mail-wm0-x243.google.com (mail-wm0-x243.google.com [IPv6:2a00:1450:400c:c09::243]) by gabe.freedesktop.org (Postfix) with ESMTPS id 798FB6E18F; Thu, 9 Nov 2017 18:51:08 +0000 (UTC) Received: by mail-wm0-x243.google.com with SMTP id s66so19083306wmf.5; Thu, 09 Nov 2017 10:51:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id; bh=/mGuuYnPtBMZ8NGr6CkQIKuO18KxYVe4ye39YozdqQg=; b=j/7F8MhA1O3qS29glcJ2PIRHIUa9jmhQXcrNtbbApscwoVP67p0Vh3cXUFXBVyFNPY 5jerSE8RGs6KQJWQFzQ3k823B/ydlyPpYjS15W+4/FD84M+PIr+4EzKK1VfmA5CETID7 b2REGEzrmABlpx0LhRzYL3zNlvbHpXwBdTIeboLyGYxXYnuWIJFPUWjW/dloBCM/ePWb jsu9qPIhV9dgkNRyqj4F0kL9lhuaHQC1Hn2vM5iZtjx59zVppOUhUHu883ltprn6RNCY PyyFFIc3Rg8QGWxXeB8FzEOdaJiv8R+BVNT4JJM/bdQ7RcJ06M0X/RubV/8kAKfnp9lF 4QuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=/mGuuYnPtBMZ8NGr6CkQIKuO18KxYVe4ye39YozdqQg=; b=J5adN764UgNvj7gE7VpioUo0BS1NtogMKGY1vIxuV84Rc1xWFCqSeVRRSO2+RQtXK/ wC5poRPg2j2lIIBcYgVKw3ZuU3mkto14z+2u5lzDTCjH3F35mfOId/R1VlJ5vnm577DX nkCVOhJKAFixeGpM57Bldb5FLFf69GSjDTUyUOwpP6JlxPn7ScZl/isCrgJAwGnPUxxF EQziadTnap8jT0jP1ScWxeG+xL641XcqVgZZmjr4jBNJthnx8Ws9jRhpKzvIxXaR9xyd CSeUSYObTKf0iER+TNKH69lf+Jds3w3pI6FmUTRReF3wbxjndo7ivTqC1Wm2GeToTgZU o7WA== X-Gm-Message-State: AJaThX4agBp5uKAauNFORgruxdTe0BN3MTOxaSkIokOEs+ZnMw54h0p+ 7khSdsAnJrUZinOQ5eILPmU= X-Google-Smtp-Source: AGs4zMYaESbEG+uyu1xeKF0aqctKvOzXOCtX0yxHN7C4tYvwVqNULV1mgL1+MH1Edrsau9EahUOxxw== X-Received: by 10.28.132.19 with SMTP id g19mr629235wmd.90.1510253467145; Thu, 09 Nov 2017 10:51:07 -0800 (PST) Received: from shalem.localdomain.com (546A5441.cm-12-3b.dynamic.ziggo.nl. [84.106.84.65]) by smtp.gmail.com with ESMTPSA id d18sm6303873wrc.14.2017.11.09.10.51.05 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Thu, 09 Nov 2017 10:51:05 -0800 (PST) From: Hans de Goede X-Google-Original-From: Hans de Goede To: Daniel Vetter , Jani Nikula , Rodrigo Vivi , Mika Kuoppala Date: Thu, 9 Nov 2017 19:51:01 +0100 Message-Id: <20171109185101.5653-1-hdegoede@redhat.com> X-Mailer: git-send-email 2.14.3 Cc: Hans de Goede , intel-gfx , dri-devel@lists.freedesktop.org Subject: [Intel-gfx] [PATCH] i915: pm: Be less agressive with clockfreq changes on Bay Trail X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Bay Trail devices are known to hang when changing the frequency often, this is discussed in great length in: https://bugzilla.kernel.org/show_bug.cgi?id=109051 Commit 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3") is an attempt to workaround this. Several users in bko109051 report that an earlier version of this patch, v1: https://bugzilla.kernel.org/attachment.cgi?id=251471 Works better for them and they still see hangs with the merged v3. Comparing the 2 versions shows that they are indeed not equivalent, v1 not only skips writing the GEN6_RP* registers from valleyview_set_rps, as v3 does. It also contained these modifications to i915_irq.c: if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) { if (!vlv_c0_above(dev_priv, &dev_priv->rps.down_ei, &now, - dev_priv->rps.down_threshold)) + VLV_RP_DOWN_EI_THRESHOLD)) events |= GEN6_PM_RP_DOWN_THRESHOLD; dev_priv->rps.down_ei = now; } if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) { if (vlv_c0_above(dev_priv, &dev_priv->rps.up_ei, &now, - dev_priv->rps.up_threshold)) + VLV_RP_UP_EI_THRESHOLD)) events |= GEN6_PM_RP_UP_THRESHOLD; dev_priv->rps.up_ei = now; } Which use less aggressive up/down thresholds, which results in less GEN6_PM_RP_*_THRESHOLD events and thus in less calls to intel_set_rps() -> valleyview_set_rps() -> vlv_punit_write(PUNIT_REG_GPU_FREQ_REQ). With the last call being the likely cause of the hang. This commit hardcodes the threshold_up and _down values for Bay Trail to less aggressive values, reducing the amount of clock frequency changes, thus avoiding the hangs some people are still seeing with the merged fix. Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=109051 Signed-off-by: Hans de Goede --- drivers/gpu/drm/i915/i915_reg.h | 3 +++ drivers/gpu/drm/i915/intel_pm.c | 5 ++++- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 68a58cce6ab1..2561af075ebb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1355,6 +1355,9 @@ enum i915_power_well_id { #define VLV_BIAS_CPU_125_SOC_875 (6 << 2) #define CHV_BIAS_CPU_50_SOC_50 (3 << 2) +#define VLV_RP_UP_EI_THRESHOLD 90 +#define VLV_RP_DOWN_EI_THRESHOLD 70 + /* vlv2 north clock has */ #define CCK_FUSE_REG 0x8 #define CCK_FUSE_HPLL_FREQ_MASK 0x3 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 01966b89be14..177b6caa0a38 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -6096,8 +6096,11 @@ static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) /* When byt can survive without system hang with dynamic * sw freq adjustments, this restriction can be lifted. */ - if (IS_VALLEYVIEW(dev_priv)) + if (IS_VALLEYVIEW(dev_priv)) { + threshold_up = VLV_RP_UP_EI_THRESHOLD; + threshold_down = VLV_RP_DOWN_EI_THRESHOLD; goto skip_hw_write; + } I915_WRITE(GEN6_RP_UP_EI, GT_INTERVAL_FROM_US(dev_priv, ei_up));