| Message ID | 20171110190845.32574-2-lionel.g.landwerlin@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, Nov 10, 2017 at 07:08:39PM +0000, Lionel Landwerlin wrote: > We were missing some registers and also can name one for which we only had > the offset. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Reviewed-by: Matthew Auld <matthew.auld@intel.com> > --- > drivers/gpu/drm/i915/i915_perf.c | 3 ++- > drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++ > 2 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 59ee808f8fd9..45aef15b9e7c 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -3023,7 +3023,8 @@ static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) > { > return gen7_is_valid_mux_addr(dev_priv, addr) || > (addr >= 0x25100 && addr <= 0x2FF90) || Maybe some define here also? - Ewelina > - addr == 0x9ec0; > + (addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) || > + addr == HSW_MBVID2_MISR0.reg; > } > > static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 6ef33422f762..8f3cf50f04b4 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1120,6 +1120,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) > /* RPC unit config (Gen8+) */ > #define RPM_CONFIG _MMIO(0x0D08) > > +/* NOA (HSW) */ > +#define HSW_MBVID2_NOA0 _MMIO(0x9E80) > +#define HSW_MBVID2_NOA1 _MMIO(0x9E84) > +#define HSW_MBVID2_NOA2 _MMIO(0x9E88) > +#define HSW_MBVID2_NOA3 _MMIO(0x9E8C) > +#define HSW_MBVID2_NOA4 _MMIO(0x9E90) > +#define HSW_MBVID2_NOA5 _MMIO(0x9E94) > +#define HSW_MBVID2_NOA6 _MMIO(0x9E98) > +#define HSW_MBVID2_NOA7 _MMIO(0x9E9C) > +#define HSW_MBVID2_NOA8 _MMIO(0x9EA0) > +#define HSW_MBVID2_NOA9 _MMIO(0x9EA4) > + > +#define HSW_MBVID2_MISR0 _MMIO(0x9EC0) > + > /* NOA (Gen8+) */ > #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4) > > -- > 2.15.0 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
Quoting Lionel Landwerlin (2017-11-10 19:08:39) > We were missing some registers and also can name one for which we only had > the offset. > > Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > Reviewed-by: Matthew Auld <matthew.auld@intel.com> > --- > drivers/gpu/drm/i915/i915_perf.c | 3 ++- > drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++ > 2 files changed, 16 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c > index 59ee808f8fd9..45aef15b9e7c 100644 > --- a/drivers/gpu/drm/i915/i915_perf.c > +++ b/drivers/gpu/drm/i915/i915_perf.c > @@ -3023,7 +3023,8 @@ static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) > { > return gen7_is_valid_mux_addr(dev_priv, addr) || > (addr >= 0x25100 && addr <= 0x2FF90) || > - addr == 0x9ec0; > + (addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) || > + addr == HSW_MBVID2_MISR0.reg; i915_mmio_reg_offset(HSW_MBVID2_NOA0) etc -Chris
On 13/11/17 11:40, Chris Wilson wrote: > Quoting Lionel Landwerlin (2017-11-10 19:08:39) >> We were missing some registers and also can name one for which we only had >> the offset. >> >> Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> >> Reviewed-by: Matthew Auld <matthew.auld@intel.com> >> --- >> drivers/gpu/drm/i915/i915_perf.c | 3 ++- >> drivers/gpu/drm/i915/i915_reg.h | 14 ++++++++++++++ >> 2 files changed, 16 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c >> index 59ee808f8fd9..45aef15b9e7c 100644 >> --- a/drivers/gpu/drm/i915/i915_perf.c >> +++ b/drivers/gpu/drm/i915/i915_perf.c >> @@ -3023,7 +3023,8 @@ static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) >> { >> return gen7_is_valid_mux_addr(dev_priv, addr) || >> (addr >= 0x25100 && addr <= 0x2FF90) || >> - addr == 0x9ec0; >> + (addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) || >> + addr == HSW_MBVID2_MISR0.reg; > i915_mmio_reg_offset(HSW_MBVID2_NOA0) etc > -Chris > Oh thanks, will send a follow up patch to clean that up.
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 59ee808f8fd9..45aef15b9e7c 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -3023,7 +3023,8 @@ static bool hsw_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) { return gen7_is_valid_mux_addr(dev_priv, addr) || (addr >= 0x25100 && addr <= 0x2FF90) || - addr == 0x9ec0; + (addr >= HSW_MBVID2_NOA0.reg && addr <= HSW_MBVID2_NOA9.reg) || + addr == HSW_MBVID2_MISR0.reg; } static bool chv_is_valid_mux_addr(struct drm_i915_private *dev_priv, u32 addr) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 6ef33422f762..8f3cf50f04b4 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -1120,6 +1120,20 @@ static inline bool i915_mmio_reg_valid(i915_reg_t reg) /* RPC unit config (Gen8+) */ #define RPM_CONFIG _MMIO(0x0D08) +/* NOA (HSW) */ +#define HSW_MBVID2_NOA0 _MMIO(0x9E80) +#define HSW_MBVID2_NOA1 _MMIO(0x9E84) +#define HSW_MBVID2_NOA2 _MMIO(0x9E88) +#define HSW_MBVID2_NOA3 _MMIO(0x9E8C) +#define HSW_MBVID2_NOA4 _MMIO(0x9E90) +#define HSW_MBVID2_NOA5 _MMIO(0x9E94) +#define HSW_MBVID2_NOA6 _MMIO(0x9E98) +#define HSW_MBVID2_NOA7 _MMIO(0x9E9C) +#define HSW_MBVID2_NOA8 _MMIO(0x9EA0) +#define HSW_MBVID2_NOA9 _MMIO(0x9EA4) + +#define HSW_MBVID2_MISR0 _MMIO(0x9EC0) + /* NOA (Gen8+) */ #define NOA_CONFIG(i) _MMIO(0x0D0C + (i) * 4)