From patchwork Tue Nov 14 23:42:23 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Rodrigo Vivi X-Patchwork-Id: 10058573 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8A28B6023A for ; Tue, 14 Nov 2017 23:42:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7C26729B23 for ; Tue, 14 Nov 2017 23:42:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6F16629B06; Tue, 14 Nov 2017 23:42:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EC55129B06 for ; Tue, 14 Nov 2017 23:42:28 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5B94289DFB; Tue, 14 Nov 2017 23:42:28 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id A299189DFB for ; Tue, 14 Nov 2017 23:42:27 +0000 (UTC) Received: from orsmga004.jf.intel.com ([10.7.209.38]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 14 Nov 2017 15:42:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.44,396,1505804400"; d="scan'208";a="149543716" Received: from rdvivi-vienna.jf.intel.com ([10.7.196.88]) by orsmga004.jf.intel.com with ESMTP; 14 Nov 2017 15:42:26 -0800 From: Rodrigo Vivi To: intel-gfx@lists.freedesktop.org Date: Tue, 14 Nov 2017 15:42:23 -0800 Message-Id: <20171114234223.10600-1-rodrigo.vivi@intel.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20171114200031.GN10981@intel.com> References: <20171114200031.GN10981@intel.com> MIME-Version: 1.0 Cc: Rodrigo Vivi Subject: [Intel-gfx] [PATCH] drm/i915/cnl: Fix wrpll math for higher freqs. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Spec describe all values in MHz. We handle our clocks in KHz. This includes the best_dco_centrality that was forgot in the same unity as spec. Consequently we couldn't get a good divider for high frequenies. Hence HDMI 2.0 wasn't working. Spec tells 999999 for initial best_dco_centrality meaning the max value in MHz. Since we convert dco from MHz to KHz we also need to convert this initial best_doc_centrality to 999999000 or 999999999 or even better, to the max that its variable allow. This patch also replaces the use of "* KHz(1)" with the values directly on KHz to avoid future confusion. v2: Use U32_MAX instead of random 99999 as spec tells. (Ville). Cc: Ville Syrjälä Cc: Shashank Sharma Cc: Mika Kahola Cc: Manasi Navare Cc: James Ausmus Signed-off-by: Rodrigo Vivi Reviewed-by: Ville Syrjälä --- drivers/gpu/drm/i915/intel_dpll_mgr.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index fba969cbda37..6cc12abdd39e 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2201,8 +2201,8 @@ cnl_ddi_calculate_wrpll(int clock, struct skl_wrpll_params *wrpll_params) { u32 afe_clock = clock * 5; - u32 dco_min = 7998 * KHz(1); - u32 dco_max = 10000 * KHz(1); + u32 dco_min = 7998000; + u32 dco_max = 10000000; u32 dco_mid = (dco_min + dco_max) / 2; static const int dividers[] = { 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 24, 28, 30, 32, 36, 40, @@ -2211,7 +2211,7 @@ cnl_ddi_calculate_wrpll(int clock, 84, 88, 90, 92, 96, 98, 100, 102, 3, 5, 7, 9, 15, 21 }; u32 dco, best_dco = 0, dco_centrality = 0; - u32 best_dco_centrality = 999999; + u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */ int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0; for (d = 0; d < ARRAY_SIZE(dividers); d++) {