From patchwork Fri Dec 8 22:38:14 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Antonio Argenziano X-Patchwork-Id: 10103401 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id AFA77602A0 for ; Fri, 8 Dec 2017 22:38:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A173228112 for ; Fri, 8 Dec 2017 22:38:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9493528D4F; Fri, 8 Dec 2017 22:38:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E6EDA28112 for ; Fri, 8 Dec 2017 22:38:34 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6CFAE6E9A1; Fri, 8 Dec 2017 22:38:34 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id DD8DE6E9A1 for ; Fri, 8 Dec 2017 22:38:32 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 08 Dec 2017 14:38:32 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,379,1508828400"; d="scan'208";a="10333362" Received: from relo-linux-2.fm.intel.com ([10.1.27.122]) by FMSMGA003.fm.intel.com with ESMTP; 08 Dec 2017 14:38:32 -0800 From: Antonio Argenziano To: intel-gfx@lists.freedesktop.org Date: Fri, 8 Dec 2017 14:38:14 -0800 Message-Id: <20171208223814.31995-1-antonio.argenziano@intel.com> X-Mailer: git-send-email 2.14.2 In-Reply-To: <20171204234541.23649-2-antonio.argenziano@intel.com> References: <20171204234541.23649-2-antonio.argenziano@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH i-g-t v3] tests/gem_exec_schedule: Add test for resetting preemptive batch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds a test that will trigger a preemption of a low priority batch by a 'bad' batch buffer which will hang. The test aims at making sure that a hanging high priority batch will not disrupt the submission flow of low priority contexts. -v2: - Rename subtest (Chris) - Use igt_hang_ctx to hang ring (Chris) - Add comment on execution order checks (Chris) -v3: - Use library call to consume hang (Chris) - Use a more explicit name for array size (Chris) Cc: Chris Wilson Cc: Michal Winiarski Signed-off-by: Antonio Argenziano Reviewed-by: Michał Winiarski --- tests/gem_exec_schedule.c | 44 +++++++++++++++++++++++++++++++++++++++++--- 1 file changed, 41 insertions(+), 3 deletions(-) diff --git a/tests/gem_exec_schedule.c b/tests/gem_exec_schedule.c index d0f85b3e..8cad15d9 100644 --- a/tests/gem_exec_schedule.c +++ b/tests/gem_exec_schedule.c @@ -41,6 +41,7 @@ #define MIN_PRIO LOCAL_I915_CONTEXT_MIN_USER_PRIORITY #define BUSY_QLEN 8 +#define MAX_ELSP_QLEN 16 IGT_TEST_DESCRIPTION("Check that we can control the order of execution"); @@ -362,7 +363,7 @@ static void preempt(int fd, unsigned ring, unsigned flags) { uint32_t result = gem_create(fd, 4096); uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ); - igt_spin_t *spin[16]; + igt_spin_t *spin[MAX_ELSP_QLEN]; uint32_t ctx[2]; igt_hang_t hang; @@ -408,7 +409,7 @@ static void preempt_other(int fd, unsigned ring) { uint32_t result = gem_create(fd, 4096); uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ); - igt_spin_t *spin[16]; + igt_spin_t *spin[MAX_ELSP_QLEN]; unsigned int other; unsigned int n, i; uint32_t ctx[3]; @@ -466,7 +467,7 @@ static void preempt_self(int fd, unsigned ring) { uint32_t result = gem_create(fd, 4096); uint32_t *ptr = gem_mmap__gtt(fd, result, 4096, PROT_READ); - igt_spin_t *spin[16]; + igt_spin_t *spin[MAX_ELSP_QLEN]; unsigned int other; unsigned int n, i; uint32_t ctx[3]; @@ -515,6 +516,40 @@ static void preempt_self(int fd, unsigned ring) gem_close(fd, result); } +static void preemptive_hang(int fd, unsigned ring) +{ + igt_spin_t *spin[MAX_ELSP_QLEN]; + igt_hang_t hang; + uint32_t ctx[2]; + + ctx[HI] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[HI], MAX_PRIO); + + for (int n = 0; n < 16; n++) { + ctx[LO] = gem_context_create(fd); + gem_context_set_priority(fd, ctx[LO], MIN_PRIO); + + spin[n] = __igt_spin_batch_new(fd, ctx[LO], ring, 0); + igt_debug("spin[%d].handle=%d\n", n, spin[n]->handle); + + gem_context_destroy(fd, ctx[LO]); + } + + hang = igt_hang_ctx(fd, ctx[HI], ring, 0, NULL); + igt_post_hang_ring(fd, hang); + + for (int n = 0; n < 16; n++) { + /* Current behavior is to execute requests in order of submission. + * This is subject to change as the scheduler evolve. The test should + * be updated to reflect such changes. + */ + igt_assert(gem_bo_busy(fd, spin[n]->handle)); + igt_spin_batch_free(fd, spin[n]); + } + + gem_context_destroy(fd, ctx[HI]); +} + static void deep(int fd, unsigned ring) { #define XS 8 @@ -1044,6 +1079,9 @@ igt_main preempt(fd, e->exec_id | e->flags, NEW_CTX | HANG_LP); } + igt_subtest_f("preemptive-hang-%s", e->name) + preemptive_hang(fd, e->exec_id | e->flags); + igt_fixture { igt_disallow_hang(fd, hang); igt_fork_hang_detector(fd);