From patchwork Mon Dec 18 15:35:17 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10120177 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 56BF060327 for ; Mon, 18 Dec 2017 15:35:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 497FF283FE for ; Mon, 18 Dec 2017 15:35:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E48228B7F; Mon, 18 Dec 2017 15:35:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id E0EDC283FE for ; Mon, 18 Dec 2017 15:35:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4D76889FC3; Mon, 18 Dec 2017 15:35:30 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga04.intel.com (mga04.intel.com [192.55.52.120]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1F4E96E1C3 for ; Mon, 18 Dec 2017 15:35:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga104.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Dec 2017 07:35:27 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.45,422,1508828400"; d="scan'208";a="3760640" Received: from delly.ld.intel.com ([10.103.238.204]) by orsmga008.jf.intel.com with ESMTP; 18 Dec 2017 07:35:26 -0800 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Mon, 18 Dec 2017 15:35:17 +0000 Message-Id: <20171218153520.14181-4-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20171218153520.14181-1-lionel.g.landwerlin@intel.com> References: <20171218153520.14181-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH 3/6] drm/i915/debugfs: add rcs topology entry X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP While the end goal is to make this information available to userspace through a new ioctl, there is no reason we can't display it in a human readable fashion through debugfs. slice0 (subslice_mask=0x7): subslice0: eu_mask: 0xff (8) subslice1: eu_mask: 0xff (8) subslice2: eu_mask: 0xff (8) subslice3: eu_mask: 0x0 (0) slice1 (subslice_mask=0x7): subslice0: eu_mask: 0xff (8) subslice1: eu_mask: 0xff (8) subslice2: eu_mask: 0xff (8) subslice3: eu_mask: 0x0 (0) slice2 (subslice_mask=0x7): subslice0: eu_mask: 0xff (8) subslice1: eu_mask: 0xff (8) subslice2: eu_mask: 0xff (8) subslice3: eu_mask: 0x0 (0) Suggested-by: Chris Wilson Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_debugfs.c | 37 +++++++++++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 6ec7543e698f..79ca6e9f9ec9 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -3173,6 +3173,42 @@ static int i915_engine_info(struct seq_file *m, void *unused) return 0; } +static int i915_rcs_topology(struct seq_file *m, void *unused) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; + int s, ss; + int subslice_stride = ALIGN(sseu->max_eus_per_subslice, 8) / 8; + int slice_stride = sseu->max_subslices * subslice_stride; + + if (sseu->max_slices == 0) { + seq_printf(m, "Unavailable\n"); + return 0; + } + + for (s = 0; s < sseu->max_slices; s++) { + seq_printf(m, "slice%i (subslice_mask=0x%x):\n", + s, sseu->subslices_mask[s]); + + for (ss = 0; ss < slice_stride / subslice_stride; ss++) { + int eu, n_subslice_eus = 0; + + seq_printf(m, "\tsubslice%i:\n", ss); + + seq_printf(m, "\t\teu_mask:"); + for (eu = 0; eu < subslice_stride; eu++) { + u8 val = sseu->eu_mask[s * slice_stride + + ss * subslice_stride + eu]; + seq_printf(m, " 0x%x", val); + n_subslice_eus += hweight8(val); + } + seq_printf(m, " (%i)\n", n_subslice_eus); + } + } + + return 0; +} + static int i915_shrinker_info(struct seq_file *m, void *unused) { struct drm_i915_private *i915 = node_to_i915(m->private); @@ -4658,6 +4694,7 @@ static const struct drm_info_list i915_debugfs_list[] = { {"i915_dmc_info", i915_dmc_info, 0}, {"i915_display_info", i915_display_info, 0}, {"i915_engine_info", i915_engine_info, 0}, + {"i915_rcs_topology", i915_rcs_topology, 0}, {"i915_shrinker_info", i915_shrinker_info, 0}, {"i915_shared_dplls_info", i915_shared_dplls_info, 0}, {"i915_dp_mst_info", i915_dp_mst_info, 0},