diff --git a/drivers/gpu/drm/i915/fixed16_16.h b/drivers/gpu/drm/i915/fixed16_16.h
index a6568df..ec859c0 100644
--- a/drivers/gpu/drm/i915/fixed16_16.h
+++ b/drivers/gpu/drm/i915/fixed16_16.h
@@ -27,26 +27,26 @@
 
 #include <linux/kernel.h>
 
-typedef struct {
-	uint32_t val;
-} uint_fixed_16_16_t;
+typedef struct fixed16_16 {
+	u32 val;
+} fixed16_16_t;
 
 #define FP_16_16_MAX ({ \
-	uint_fixed_16_16_t fp; \
+	fixed16_16_t fp; \
 	fp.val = UINT_MAX; \
 	fp; \
 })
 
-static inline bool is_fixed16_zero(uint_fixed_16_16_t val)
+static inline bool is_fixed16_zero(fixed16_16_t val)
 {
 	if (val.val == 0)
 		return true;
 	return false;
 }
 
-static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
+static inline fixed16_16_t u32_to_fixed16(u32 val)
 {
-	uint_fixed_16_16_t fp;
+	fixed16_16_t fp;
 
 	WARN_ON(val > U16_MAX);
 
@@ -54,115 +54,106 @@ static inline uint_fixed_16_16_t u32_to_fixed16(uint32_t val)
 	return fp;
 }
 
-static inline uint32_t fixed16_to_u32_round_up(uint_fixed_16_16_t fp)
+static inline u32 fixed16_to_u32_round_up(fixed16_16_t fp)
 {
 	return DIV_ROUND_UP(fp.val, 1 << 16);
 }
 
-static inline uint32_t fixed16_to_u32(uint_fixed_16_16_t fp)
+static inline u32 fixed16_to_u32(fixed16_16_t fp)
 {
 	return fp.val >> 16;
 }
 
-static inline uint_fixed_16_16_t min_fixed16(uint_fixed_16_16_t min1,
-					     uint_fixed_16_16_t min2)
+static inline fixed16_16_t min_fixed16(fixed16_16_t min1, fixed16_16_t min2)
 {
-	uint_fixed_16_16_t min;
+	fixed16_16_t min;
 
 	min.val = min(min1.val, min2.val);
 	return min;
 }
 
-static inline uint_fixed_16_16_t max_fixed16(uint_fixed_16_16_t max1,
-					     uint_fixed_16_16_t max2)
+static inline fixed16_16_t max_fixed16(fixed16_16_t max1, fixed16_16_t max2)
 {
-	uint_fixed_16_16_t max;
+	fixed16_16_t max;
 
 	max.val = max(max1.val, max2.val);
 	return max;
 }
 
-static inline uint_fixed_16_16_t clamp_u64_to_fixed16(uint64_t val)
+static inline fixed16_16_t clamp_u64_to_fixed16(u64 val)
 {
-	uint_fixed_16_16_t fp;
+	fixed16_16_t fp;
 
 	WARN_ON(val > U32_MAX);
-	fp.val = (uint32_t) val;
+	fp.val = (u32) val;
 	return fp;
 }
 
-static inline uint32_t div_round_up_fixed16(uint_fixed_16_16_t val,
-					    uint_fixed_16_16_t d)
+static inline u32 div_round_up_fixed16(fixed16_16_t val, fixed16_16_t d)
 {
 	return DIV_ROUND_UP(val.val, d.val);
 }
 
-static inline uint32_t mul_round_up_u32_fixed16(uint32_t val,
-						uint_fixed_16_16_t mul)
+static inline u32 mul_round_up_u32_fixed16(u32 val, fixed16_16_t mul)
 {
-	uint64_t intermediate_val;
+	u64 intermediate_val;
 
-	intermediate_val = (uint64_t) val * mul.val;
+	intermediate_val = (u64) val * mul.val;
 	intermediate_val = DIV_ROUND_UP_ULL(intermediate_val, 1 << 16);
 	WARN_ON(intermediate_val > U32_MAX);
-	return (uint32_t) intermediate_val;
+	return (u32) intermediate_val;
 }
 
-static inline uint_fixed_16_16_t mul_fixed16(uint_fixed_16_16_t val,
-					     uint_fixed_16_16_t mul)
+static inline fixed16_16_t mul_fixed16(fixed16_16_t val, fixed16_16_t mul)
 {
-	uint64_t intermediate_val;
+	u64 intermediate_val;
 
-	intermediate_val = (uint64_t) val.val * mul.val;
+	intermediate_val = (u64) val.val * mul.val;
 	intermediate_val = intermediate_val >> 16;
 	return clamp_u64_to_fixed16(intermediate_val);
 }
 
-static inline uint_fixed_16_16_t div_fixed16(uint32_t val, uint32_t d)
+static inline fixed16_16_t div_fixed16(u32 val, u32 d)
 {
-	uint64_t interm_val;
+	u64 interm_val;
 
-	interm_val = (uint64_t)val << 16;
+	interm_val = (u64)val << 16;
 	interm_val = DIV_ROUND_UP_ULL(interm_val, d);
 	return clamp_u64_to_fixed16(interm_val);
 }
 
-static inline uint32_t div_round_up_u32_fixed16(uint32_t val,
-						uint_fixed_16_16_t d)
+static inline u32 div_round_up_u32_fixed16(u32 val, fixed16_16_t d)
 {
-	uint64_t interm_val;
+	u64 interm_val;
 
-	interm_val = (uint64_t)val << 16;
+	interm_val = (u64)val << 16;
 	interm_val = DIV_ROUND_UP_ULL(interm_val, d.val);
 	WARN_ON(interm_val > U32_MAX);
-	return (uint32_t) interm_val;
+	return (u32) interm_val;
 }
 
-static inline uint_fixed_16_16_t mul_u32_fixed16(uint32_t val,
-						 uint_fixed_16_16_t mul)
+static inline fixed16_16_t mul_u32_fixed16(u32 val, fixed16_16_t mul)
 {
-	uint64_t intermediate_val;
+	u64 intermediate_val;
 
-	intermediate_val = (uint64_t) val * mul.val;
+	intermediate_val = (u64) val * mul.val;
 	return clamp_u64_to_fixed16(intermediate_val);
 }
 
-static inline uint_fixed_16_16_t add_fixed16(uint_fixed_16_16_t add1,
-					     uint_fixed_16_16_t add2)
+static inline fixed16_16_t add_fixed16(fixed16_16_t add1, fixed16_16_t add2)
 {
-	uint64_t interm_sum;
+	u64 interm_sum;
 
-	interm_sum = (uint64_t) add1.val + add2.val;
+	interm_sum = (u64) add1.val + add2.val;
 	return clamp_u64_to_fixed16(interm_sum);
 }
 
-static inline uint_fixed_16_16_t add_fixed16_u32(uint_fixed_16_16_t add1,
-						 uint32_t add2)
+static inline fixed16_16_t add_fixed16_u32(fixed16_16_t add1, u32 add2)
 {
-	uint64_t interm_sum;
-	uint_fixed_16_16_t interm_add2 = u32_to_fixed16(add2);
+	u64 interm_sum;
+	fixed16_16_t interm_add2 = u32_to_fixed16(add2);
 
-	interm_sum = (uint64_t) add1.val + interm_add2.val;
+	interm_sum = (u64)add1.val + interm_add2.val;
 	return clamp_u64_to_fixed16(interm_sum);
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0a7d094..802260c 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1320,8 +1320,8 @@ struct skl_wm_params {
 	uint32_t plane_pixel_rate;
 	uint32_t y_min_scanlines;
 	uint32_t plane_bytes_per_line;
-	uint_fixed_16_16_t plane_blocks_per_line;
-	uint_fixed_16_16_t y_tile_minimum;
+	fixed16_16_t plane_blocks_per_line;
+	fixed16_16_t y_tile_minimum;
 	uint32_t linetime_us;
 };
 
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 1db79a8..5dccbf9 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3867,14 +3867,14 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
  * Return value is provided in 16.16 fixed point form to retain fractional part.
  * Caller should take care of dividing & rounding off the value.
  */
-static uint_fixed_16_16_t
+static fixed16_16_t
 skl_plane_downscale_amount(const struct intel_crtc_state *cstate,
 			   const struct intel_plane_state *pstate)
 {
 	struct intel_plane *plane = to_intel_plane(pstate->base.plane);
 	uint32_t src_w, src_h, dst_w, dst_h;
-	uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
-	uint_fixed_16_16_t downscale_h, downscale_w;
+	fixed16_16_t fp_w_ratio, fp_h_ratio;
+	fixed16_16_t downscale_h, downscale_w;
 
 	if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
 		return u32_to_fixed16(0);
@@ -3909,10 +3909,10 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 	return mul_fixed16(downscale_w, downscale_h);
 }
 
-static uint_fixed_16_16_t
+static fixed16_16_t
 skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state)
 {
-	uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1);
+	fixed16_16_t pipe_downscale = u32_to_fixed16(1);
 
 	if (!crtc_state->base.enable)
 		return pipe_downscale;
@@ -3920,8 +3920,8 @@ void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
 	if (crtc_state->pch_pfit.enabled) {
 		uint32_t src_w, src_h, dst_w, dst_h;
 		uint32_t pfit_size = crtc_state->pch_pfit.size;
-		uint_fixed_16_16_t fp_w_ratio, fp_h_ratio;
-		uint_fixed_16_16_t downscale_h, downscale_w;
+		fixed16_16_t fp_w_ratio, fp_h_ratio;
+		fixed16_16_t downscale_h, downscale_w;
 
 		src_w = crtc_state->pipe_src_w;
 		src_h = crtc_state->pipe_src_h;
@@ -3953,15 +3953,15 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	struct intel_plane_state *intel_pstate;
 	int crtc_clock, dotclk;
 	uint32_t pipe_max_pixel_rate;
-	uint_fixed_16_16_t pipe_downscale;
-	uint_fixed_16_16_t max_downscale = u32_to_fixed16(1);
+	fixed16_16_t pipe_downscale;
+	fixed16_16_t max_downscale = u32_to_fixed16(1);
 
 	if (!cstate->base.enable)
 		return 0;
 
 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) {
-		uint_fixed_16_16_t plane_downscale;
-		uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8);
+		fixed16_16_t plane_downscale;
+		fixed16_16_t fp_9_div_8 = div_fixed16(9, 8);
 		int bpp;
 
 		if (!intel_wm_plane_visible(cstate,
@@ -4012,7 +4012,7 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	uint32_t width = 0, height = 0;
 	struct drm_framebuffer *fb;
 	u32 format;
-	uint_fixed_16_16_t down_scale_amount;
+	fixed16_16_t down_scale_amount;
 
 	if (!intel_pstate->base.visible)
 		return 0;
@@ -4309,12 +4309,12 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
  * should allow pixel_rate up to ~2 GHz which seems sufficient since max
  * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
 */
-static uint_fixed_16_16_t
+static fixed16_16_t
 skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate,
 	       uint8_t cpp, uint32_t latency)
 {
 	uint32_t wm_intermediate_val;
-	uint_fixed_16_16_t ret;
+	fixed16_16_t ret;
 
 	if (latency == 0)
 		return FP_16_16_MAX;
@@ -4328,13 +4328,13 @@ int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc,
 	return ret;
 }
 
-static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
-			uint32_t pipe_htotal,
-			uint32_t latency,
-			uint_fixed_16_16_t plane_blocks_per_line)
+static fixed16_16_t skl_wm_method2(uint32_t pixel_rate,
+				   uint32_t pipe_htotal,
+				   uint32_t latency,
+				   fixed16_16_t plane_blocks_per_line)
 {
 	uint32_t wm_intermediate_val;
-	uint_fixed_16_16_t ret;
+	fixed16_16_t ret;
 
 	if (latency == 0)
 		return FP_16_16_MAX;
@@ -4346,12 +4346,12 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
 	return ret;
 }
 
-static uint_fixed_16_16_t
+static fixed16_16_t
 intel_get_linetime_us(struct intel_crtc_state *cstate)
 {
 	uint32_t pixel_rate;
 	uint32_t crtc_htotal;
-	uint_fixed_16_16_t linetime_us;
+	fixed16_16_t linetime_us;
 
 	if (!cstate->base.active)
 		return u32_to_fixed16(0);
@@ -4372,7 +4372,7 @@ static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate,
 			      const struct intel_plane_state *pstate)
 {
 	uint64_t adjusted_pixel_rate;
-	uint_fixed_16_16_t downscale_amount;
+	fixed16_16_t downscale_amount;
 
 	/* Shouldn't reach here on disabled planes... */
 	if (WARN_ON(!intel_wm_plane_visible(cstate, pstate)))
@@ -4491,8 +4491,8 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 {
 	const struct drm_plane_state *pstate = &intel_pstate->base;
 	uint32_t latency = dev_priv->wm.skl_latency[level];
-	uint_fixed_16_16_t method1, method2;
-	uint_fixed_16_16_t selected_result;
+	fixed16_16_t method1, method2;
+	fixed16_16_t selected_result;
 	uint32_t res_blocks, res_lines;
 	struct intel_atomic_state *state =
 		to_intel_atomic_state(cstate->base.state);
@@ -4626,7 +4626,7 @@ static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
 {
 	struct drm_atomic_state *state = cstate->base.state;
 	struct drm_i915_private *dev_priv = to_i915(state->dev);
-	uint_fixed_16_16_t linetime_us;
+	fixed16_16_t linetime_us;
 	uint32_t linetime_wm;
 
 	linetime_us = intel_get_linetime_us(cstate);
