From patchwork Fri Jan 12 16:00:34 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10161291 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6CDA7602B3 for ; Fri, 12 Jan 2018 16:00:51 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5DA59288C5 for ; Fri, 12 Jan 2018 16:00:51 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 527A5288D8; Fri, 12 Jan 2018 16:00:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 0F1B9288C5 for ; Fri, 12 Jan 2018 16:00:51 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5CA3A6E7D0; Fri, 12 Jan 2018 16:00:48 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by gabe.freedesktop.org (Postfix) with ESMTPS id BA3AE6E7CB for ; Fri, 12 Jan 2018 16:00:46 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga104.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Jan 2018 08:00:46 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,349,1511856000"; d="scan'208";a="20482105" Received: from delly.ld.intel.com ([10.103.238.204]) by fmsmga004.fm.intel.com with ESMTP; 12 Jan 2018 08:00:44 -0800 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Fri, 12 Jan 2018 16:00:34 +0000 Message-Id: <20180112160036.25846-5-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180112160036.25846-1-lionel.g.landwerlin@intel.com> References: <20180112160036.25846-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH v3 4/6] drm/i915: add rcs topology to error state X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This might be useful information for developers looking at an error state. v2: Place topology towards the end of the error state (Chris) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_gpu_error.c | 40 +++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_gpu_error.c b/drivers/gpu/drm/i915/i915_gpu_error.c index 944059322daa..cc7f53cc9a77 100644 --- a/drivers/gpu/drm/i915/i915_gpu_error.c +++ b/drivers/gpu/drm/i915/i915_gpu_error.c @@ -605,6 +605,45 @@ static void err_print_uc(struct drm_i915_error_state_buf *m, print_error_obj(m, NULL, "GuC log buffer", error_uc->guc_log); } +static void err_print_rcs_topology(struct drm_i915_error_state_buf *m, + const struct sseu_dev_info *sseu) +{ + int s, ss; + int subslice_stride = + DIV_ROUND_UP(sseu->max_eus_per_subslice, BITS_PER_BYTE); + + /* Unavailable prior to Gen 8. */ + if (sseu->max_slices == 0) + return; + + err_printf(m, "RCS topology:\n"); + + for (s = 0; s < sseu->max_slices; s++) { + err_printf(m, " slice%i %u subslice(s) (0x%hhx):\n", + s, hweight8(sseu->subslice_mask[s]), + sseu->subslice_mask[s]); + + for (ss = 0; ss < sseu->max_subslices; ss++) { + int eu_group, n_subslice_eus = 0; + + for (eu_group = 0; eu_group < subslice_stride; eu_group++) { + n_subslice_eus += + hweight8(sseu_eu_mask(sseu, s, ss, eu_group)); + } + + err_printf(m, " subslice%i: %u EUs (", ss, n_subslice_eus); + for (eu_group = 0; + eu_group < max(0, subslice_stride - 1); + eu_group++) { + u8 val = sseu_eu_mask(sseu, s, ss, eu_group); + err_printf(m, " 0x%hhx", val); + } + err_printf(m, "0x%hhx)\n", + sseu_eu_mask(sseu, s, ss, subslice_stride - 1)); + } + } +} + int i915_error_state_to_str(struct drm_i915_error_state_buf *m, const struct i915_gpu_state *error) { @@ -787,6 +826,7 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, intel_display_print_error_state(m, error->display); err_print_capabilities(m, &error->device_info); + err_print_rcs_topology(m, &INTEL_INFO(dev_priv)->sseu); err_print_params(m, &error->params); err_print_uc(m, &error->uc);