From patchwork Tue Jan 16 13:40:10 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lionel Landwerlin X-Patchwork-Id: 10167007 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9EAC3601E7 for ; Tue, 16 Jan 2018 13:40:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 93910285A5 for ; Tue, 16 Jan 2018 13:40:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8832228595; Tue, 16 Jan 2018 13:40:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A683F285BD for ; Tue, 16 Jan 2018 13:40:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4FE4789BF6; Tue, 16 Jan 2018 13:40:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 87C3989BF4 for ; Tue, 16 Jan 2018 13:40:21 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 16 Jan 2018 05:40:21 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,368,1511856000"; d="scan'208";a="22047894" Received: from delly.ld.intel.com ([10.103.238.204]) by fmsmga004.fm.intel.com with ESMTP; 16 Jan 2018 05:40:20 -0800 From: Lionel Landwerlin To: intel-gfx@lists.freedesktop.org Date: Tue, 16 Jan 2018 13:40:10 +0000 Message-Id: <20180116134010.20307-7-lionel.g.landwerlin@intel.com> X-Mailer: git-send-email 2.15.1 In-Reply-To: <20180116134010.20307-1-lionel.g.landwerlin@intel.com> References: <20180116134010.20307-1-lionel.g.landwerlin@intel.com> Subject: [Intel-gfx] [PATCH v5 6/6] drm/i915: expose rcs topology through query uAPI X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP With the introduction of asymmetric slices in CNL, we cannot rely on the previous SUBSLICE_MASK getparam to tell userspace what subslices are available. Here we introduce a more detailed way of querying the Gen's GPU topology that doesn't aggregate numbers. This is essential for monitoring parts of the GPU with the OA unit, because counters need to be normalized to the number of EUs/subslices/slices. The current aggregated numbers like EU_TOTAL do not gives us sufficient information. As a bonus we can draw representations of the GPU : https://imgur.com/a/vuqpa v2: Rename uapi struct s/_mask/_info/ (Tvrtko) Report max_slice/subslice/eus_per_subslice rather than strides (Tvrtko) Add uapi macros to read data from *_info structs (Tvrtko) v3: Use !!(v & DRM_I915_BIT()) for uapi macros instead of custom shifts (Tvrtko) v4: factorize query item writting (Tvrtko) tweak uapi struct/define names (Tvrtko) Signed-off-by: Lionel Landwerlin --- drivers/gpu/drm/i915/i915_query.c | 107 ++++++++++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 53 +++++++++++++++++++ 2 files changed, 160 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 5694cfea4553..4d18fbd07cbd 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -25,8 +25,102 @@ #include "i915_drv.h" #include +static int copy_query_data(struct drm_i915_query_item *query_item, + const void *item_ptr, u32 item_length, + const void *data_ptr, u32 data_length) +{ + u32 total_length = item_length + data_length; + + if (query_item->length == 0) { + query_item->length = total_length; + return 0; + } + + if (query_item->length != total_length) + return -EINVAL; + + if (copy_to_user(u64_to_user_ptr(query_item->data_ptr), + item_ptr, item_length)) + return -EFAULT; + + if (copy_to_user(u64_to_user_ptr(query_item->data_ptr + item_length), + data_ptr, data_length)) + return -EFAULT; + + return 0; +} + +static int query_slice_info(struct drm_i915_private *dev_priv, + struct drm_i915_query_item *query_item) +{ + const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; + struct drm_i915_query_slice_info slice_info; + + if (sseu->max_slices == 0) + return -ENODEV; + + /* + * If we ever change the internal slice mask data type, we'll need to + * update this function. + */ + BUILD_BUG_ON(sizeof(u8) != sizeof(sseu->slice_mask)); + + memset(&slice_info, 0, sizeof(slice_info)); + slice_info.max_slices = sseu->max_slices; + + return copy_query_data(query_item, &slice_info, sizeof(slice_info), + &sseu->slice_mask, sizeof(sseu->slice_mask)); +} + +static int query_subslice_info(struct drm_i915_private *dev_priv, + struct drm_i915_query_item *query_item) +{ + const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; + struct drm_i915_query_subslice_info subslice_info; + u32 data_length; + + if (sseu->max_slices == 0) + return -ENODEV; + + memset(&subslice_info, 0, sizeof(subslice_info)); + subslice_info.max_slices = sseu->max_slices; + subslice_info.max_subslices = sseu->max_subslices; + + data_length = subslice_info.max_slices * + DIV_ROUND_UP(subslice_info.max_subslices, + sizeof(sseu->subslice_mask[0]) * BITS_PER_BYTE); + + return copy_query_data(query_item, + &subslice_info, sizeof(subslice_info), + sseu->subslice_mask, data_length); +} + +static int query_eu_info(struct drm_i915_private *dev_priv, + struct drm_i915_query_item *query_item) +{ + const struct sseu_dev_info *sseu = &INTEL_INFO(dev_priv)->sseu; + struct drm_i915_query_eu_info eu_info; + u32 data_length; + + if (sseu->max_slices == 0) + return -ENODEV; + + memset(&eu_info, 0, sizeof(eu_info)); + eu_info.max_slices = sseu->max_slices; + eu_info.max_subslices = sseu->max_subslices; + eu_info.max_eus_per_subslice = sseu->max_eus_per_subslice; + + data_length = eu_info.max_slices * eu_info.max_subslices * + DIV_ROUND_UP(eu_info.max_eus_per_subslice, BITS_PER_BYTE); + + return copy_query_data(query_item, + &eu_info, sizeof(eu_info), + sseu->eu_mask, data_length); +} + int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) { + struct drm_i915_private *dev_priv = to_i915(dev); struct drm_i915_query *args = data; struct drm_i915_query_item __user *user_item_ptr = u64_to_user_ptr(args->items_ptr); @@ -34,15 +128,28 @@ int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) for (i = 0; i < args->num_items; i++, user_item_ptr++) { struct drm_i915_query_item item; + int ret; if (copy_from_user(&item, user_item_ptr, sizeof(item))) return -EFAULT; switch (item.query_id) { + case DRM_I915_QUERY_SLICE_INFO: + ret = query_slice_info(dev_priv, &item); + break; + case DRM_I915_QUERY_SUBSLICE_INFO: + ret = query_subslice_info(dev_priv, &item); + break; + case DRM_I915_QUERY_EU_INFO: + ret = query_eu_info(dev_priv, &item); + break; default: return -EINVAL; } + if (ret) + return ret; + if (copy_to_user(user_item_ptr, &item, sizeof(item))) return -EFAULT; } diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 39e93f10f2cd..005a293283ec 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1618,6 +1618,9 @@ struct drm_i915_perf_oa_config { struct drm_i915_query_item { __u64 query_id; +#define DRM_I915_QUERY_SLICE_INFO 0x01 +#define DRM_I915_QUERY_SUBSLICE_INFO 0x02 +#define DRM_I915_QUERY_EU_INFO 0x03 /* * When set to zero by userspace, this is filled with the size of the @@ -1644,6 +1647,56 @@ struct drm_i915_query { __u64 items_ptr; }; +#define DRM_I915_BIT(bit) (1 << (bit)) + +/* Data written by the kernel with query DRM_I915_QUERY_ID_SLICES_INFO : + * + * data: each bit indicates whether a slice is available (1) or fused off (0). + * Use DRM_I915_QUERY_SLICE_AVAILABLE() to query a given slice's + * availability. + */ +struct drm_i915_query_slice_info { + __u32 max_slices; + +#define DRM_I915_QUERY_SLICE_AVAILABLE(info, slice) \ + !!((info)->data[(slice) / 8] & DRM_I915_BIT((slice) % 8)) + __u8 data[]; +}; + +/* Data written by the kernel with query DRM_I915_QUERY_ID_SUBSLICES_INFO : + * + * data: each bit indicates whether a subslice is available (1) or fused off + * (0). Use DRM_I915_QUERY_SUBSLICE_AVAILABLE() to query a given + * subslice's availability. + */ +struct drm_i915_query_subslice_info { + __u32 max_slices; + __u32 max_subslices; + +#define DRM_I915_QUERY_SUBSLICE_AVAILABLE(info, slice, subslice) \ + !!((info)->data[(slice) * ALIGN((info)->max_subslices, 8) / 8 + \ + (subslice) / 8] & DRM_I915_BIT((subslice) % 8)) + __u8 data[]; +}; + +/* Data written by the kernel with query DRM_I915_QUERY_ID_EUS_INFO : + * + * data: Each bit indicates whether a subslice is available (1) or fused off + * (0). Use DRM_I915_QUERY_EU_AVAILABLE() to query a given EU's + * availability. + */ +struct drm_i915_query_eu_info { + __u32 max_slices; + __u32 max_subslices; + __u32 max_eus_per_subslice; + +#define DRM_I915_QUERY_EU_AVAILABLE(info, slice, subslice, eu) \ + !!((info)->data[(slice) * ALIGN((info)->max_eus_per_subslice, 8) / 8 * (info)->max_subslices + \ + (subslice) * ALIGN((info)->max_eus_per_subslice, 8) / 8 + \ + (eu) / 8] & DRM_I915_BIT((eu) % 8)) + __u8 data[]; +}; + #if defined(__cplusplus) } #endif