| Message ID | 20180123190536.11208-10-paulo.r.zanoni@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Jan 23, 2018 at 05:05:28PM -0200, Paulo Zanoni wrote: > From: Mahesh Kumar <mahesh1.kumar@intel.com> > > This patch introduce MBus control registers and their bit-fields > MBUS_ABOX_CTL > MBUS_BBOX_CTL > MBUS_DBOX_CTL > MBUS_UBOX_CTL > > Changes Since V1: > - Use function like macros (Paulo) > - fix copy-paste error (Paulo) > > Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: James Ausmus <james.ausmus@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 25 +++++++++++++++++++++++++ > 1 file changed, 25 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 1746df9a263d..0cb77cd18cdb 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2679,6 +2679,31 @@ enum i915_power_well_id { > #define LM_FIFO_WATERMARK 0x0000001F > #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ > > +#define MBUS_ABOX_CTL _MMIO(0x45038) > +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) > +#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) > +#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) > +#define MBUS_ABOX_B_CREDIT(x) ((x) << 16) > +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) > +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) > +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) > +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) > + > +#define _PIPEA_MBUS_DBOX_CTL 0x7003C > +#define _PIPEB_MBUS_DBOX_CTL 0x7103C > +#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ > + _PIPEB_MBUS_DBOX_CTL) > +#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) > +#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) > +#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) > +#define MBUS_DBOX_B_CREDIT(x) ((x) << 8) > +#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) > +#define MBUS_DBOX_A_CREDIT(x) ((x) << 0) > + > +#define MBUS_UBOX_CTL _MMIO(0x4503C) > +#define MBUS_BBOX_CTL_S1 _MMIO(0x45040) > +#define MBUS_BBOX_CTL_S2 _MMIO(0x45044) > + > /* Make render/texture TLB fetches lower priorty than associated data > * fetches. This is not turned on by default > */ > -- > 2.14.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 1746df9a263d..0cb77cd18cdb 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2679,6 +2679,31 @@ enum i915_power_well_id { #define LM_FIFO_WATERMARK 0x0000001F #define MI_ARB_STATE _MMIO(0x20e4) /* 915+ only */ +#define MBUS_ABOX_CTL _MMIO(0x45038) +#define MBUS_ABOX_BW_CREDIT_MASK (3 << 20) +#define MBUS_ABOX_BW_CREDIT(x) ((x) << 20) +#define MBUS_ABOX_B_CREDIT_MASK (0xF << 16) +#define MBUS_ABOX_B_CREDIT(x) ((x) << 16) +#define MBUS_ABOX_BT_CREDIT_POOL2_MASK (0x1F << 8) +#define MBUS_ABOX_BT_CREDIT_POOL2(x) ((x) << 8) +#define MBUS_ABOX_BT_CREDIT_POOL1_MASK (0x1F << 0) +#define MBUS_ABOX_BT_CREDIT_POOL1(x) ((x) << 0) + +#define _PIPEA_MBUS_DBOX_CTL 0x7003C +#define _PIPEB_MBUS_DBOX_CTL 0x7103C +#define PIPE_MBUS_DBOX_CTL(pipe) _MMIO_PIPE(pipe, _PIPEA_MBUS_DBOX_CTL, \ + _PIPEB_MBUS_DBOX_CTL) +#define MBUS_DBOX_BW_CREDIT_MASK (3 << 14) +#define MBUS_DBOX_BW_CREDIT(x) ((x) << 14) +#define MBUS_DBOX_B_CREDIT_MASK (0x1F << 8) +#define MBUS_DBOX_B_CREDIT(x) ((x) << 8) +#define MBUS_DBOX_A_CREDIT_MASK (0xF << 0) +#define MBUS_DBOX_A_CREDIT(x) ((x) << 0) + +#define MBUS_UBOX_CTL _MMIO(0x4503C) +#define MBUS_BBOX_CTL_S1 _MMIO(0x45040) +#define MBUS_BBOX_CTL_S2 _MMIO(0x45044) + /* Make render/texture TLB fetches lower priorty than associated data * fetches. This is not turned on by default */