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[15/17] drm/i915/gen11: fix the SAGV block time for gen11

Message ID 20180123190536.11208-16-paulo.r.zanoni@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Zanoni, Paulo R Jan. 23, 2018, 7:05 p.m. UTC 
It's 10us for gen 11.

Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

Comments

James Ausmus Jan. 25, 2018, 11:09 p.m. UTC | #1 
On Tue, Jan 23, 2018 at 05:05:34PM -0200, Paulo Zanoni wrote:
> It's 10us for gen 11.
> 
> Reviewed-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Reviewed-by: James Ausmus <james.ausmus@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_pm.c | 9 ++++++++-
>  1 file changed, 8 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 84a5b13fdee2..1edd1445ab5b 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -3711,11 +3711,18 @@ bool intel_can_enable_sagv(struct drm_atomic_state *state)
>  	struct intel_crtc_state *cstate;
>  	enum pipe pipe;
>  	int level, latency;
> -	int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
> +	int sagv_block_time_us;
>  
>  	if (!intel_has_sagv(dev_priv))
>  		return false;
>  
> +	if (IS_GEN9(dev_priv))
> +		sagv_block_time_us = 30;
> +	else if (IS_GEN10(dev_priv))
> +		sagv_block_time_us = 20;
> +	else
> +		sagv_block_time_us = 10;
> +
>  	/*
>  	 * SKL+ workaround: bspec recommends we disable the SAGV when we have
>  	 * more then one pipe enabled
> -- 
> 2.14.3
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 84a5b13fdee2..1edd1445ab5b 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -3711,11 +3711,18 @@  bool intel_can_enable_sagv(struct drm_atomic_state *state)
 	struct intel_crtc_state *cstate;
 	enum pipe pipe;
 	int level, latency;
-	int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20;
+	int sagv_block_time_us;
 
 	if (!intel_has_sagv(dev_priv))
 		return false;
 
+	if (IS_GEN9(dev_priv))
+		sagv_block_time_us = 30;
+	else if (IS_GEN10(dev_priv))
+		sagv_block_time_us = 20;
+	else
+		sagv_block_time_us = 10;
+
 	/*
 	 * SKL+ workaround: bspec recommends we disable the SAGV when we have
 	 * more then one pipe enabled