From patchwork Tue Feb 13 21:46:13 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Dhinakaran Pandiyan X-Patchwork-Id: 10217631 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 58648601C2 for ; Tue, 13 Feb 2018 21:46:22 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47BC928D01 for ; Tue, 13 Feb 2018 21:46:22 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3B92928D54; Tue, 13 Feb 2018 21:46:22 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A79A328D01 for ; Tue, 13 Feb 2018 21:46:21 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C3A346E049; Tue, 13 Feb 2018 21:46:20 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by gabe.freedesktop.org (Postfix) with ESMTPS id 237AE6E049 for ; Tue, 13 Feb 2018 21:46:19 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga007.jf.intel.com ([10.7.209.58]) by fmsmga103.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 13 Feb 2018 13:46:17 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.46,509,1511856000"; d="scan'208";a="17416326" Received: from dk-thinkpad-x260.jf.intel.com ([10.54.75.38]) by orsmga007.jf.intel.com with ESMTP; 13 Feb 2018 13:46:16 -0800 From: Dhinakaran Pandiyan To: intel-gfx@lists.freedesktop.org Date: Tue, 13 Feb 2018 13:46:13 -0800 Message-Id: <20180213214613.3936-1-dhinakaran.pandiyan@intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <151842803599.18923.7772336419122374756@mail.alporthouse.com> References: <151842803599.18923.7772336419122374756@mail.alporthouse.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2] drm/i915/psr: HW tracking for cursor moves to fix lags. X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP DRM_IOCTL_MODE_CURSOR results in a frontbuffer flush before the cursor plane MMIOs are written to. But this flush is not necessary for PSR as hardware tracking takes care of exiting PSR when the MMIO's are written. Introduce a new fb_op_origin enum to differentiate flushes due to a BO being pinned from those originating due to a dirty fbdev buffer. Now, this enum can be ignored in psr_flush and psr_invalidate. v2: Update comment in i915_gem_object_pin_to_display_plane. (Chris) Cc: Rodrigo Vivi Cc: Ville Syrjälä Cc: Chris Wilson Signed-off-by: Dhinakaran Pandiyan --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_gem.c | 11 +++++++++-- drivers/gpu/drm/i915/intel_psr.c | 6 ++++-- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 81886b74c750..3bf6c6ec0509 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -637,6 +637,7 @@ enum fb_op_origin { ORIGIN_CS, ORIGIN_FLIP, ORIGIN_DIRTYFB, + ORIGIN_PINNEDFB, }; struct intel_fbc { diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index fc68b35854df..405acf3562de 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -4139,9 +4139,16 @@ i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, vma->display_alignment = max_t(u64, vma->display_alignment, alignment); - /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */ + /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() to + * flush the caches. + */ __i915_gem_object_flush_for_display(obj); - intel_fb_obj_flush(obj, ORIGIN_DIRTYFB); + + /* Features like PSR might want to rely on HW to do the frontbuffer + * flush, pass origin as ORIGIN_PINNEDFB rather than ORIGIN_DIRTYFB + * so that their flush implementations can handle it accordingly. + */ + intel_fb_obj_flush(obj, ORIGIN_PINNEDFB); /* It should now be out of any other write domains, and we can update * the domain values for our changes. diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 2a31c7cbdb41..ddfabdff3dea 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -842,7 +842,8 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, if (!CAN_PSR(dev_priv)) return; - if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP) + if (dev_priv->psr.has_hw_tracking && + (origin == ORIGIN_FLIP || origin == ORIGIN_PINNEDFB)) return; mutex_lock(&dev_priv->psr.lock); @@ -885,7 +886,8 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, if (!CAN_PSR(dev_priv)) return; - if (dev_priv->psr.has_hw_tracking && origin == ORIGIN_FLIP) + if (dev_priv->psr.has_hw_tracking && + (origin == ORIGIN_FLIP || origin == ORIGIN_PINNEDFB)) return; mutex_lock(&dev_priv->psr.lock);