| Message ID | 20180214141213.24140-1-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
Quoting Mika Kuoppala (2018-02-14 14:12:13) > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > v2: Rebase. > > v3: > * Remove DPF, it has been removed from SKL+. > * Fix -internal rebase wrt. execlists interrupt handling. > > v4: Rebase. > > v5: > * Updated for POR changes. (Daniele Ceraolo Spurio) > * Merged with irq handling fixes by Daniele Ceraolo Spurio: > * Simplify the code by using gen8_cs_irq_handler. > * Fix interrupt handling for the upstream kernel. > > v6: > * Remove early bringup debug messages (Tvrtko) > * Add NB about arbitrary spin wait timeout (Tvrtko) > > v7 (from Paulo): > * Don't try to write RO bits to registers. > * Don't check for PCH types that don't exist. PCH interrupts are not > here yet. > > v9: > * squashed in selector and shared register handling (Daniele) > * skip writing of irq if data is not valid (Daniele) > * use time_after32 (Chris) > * use I915_MAX_VCS and I915_MAX_VECS (Daniele) > * remove fake pm interrupt handling for later patch (Mika) > > Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Cc: Chris Wilson <chris@chris-wilson.co.uk> > Cc: Oscar Mateo <oscar.mateo@intel.com> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 212 ++++++++++++++++++++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_pm.c | 7 +- > 2 files changed, 218 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index b886bd459acc..9a2d12c8c44c 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -408,6 +408,37 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) > spin_unlock_irq(&dev_priv->irq_lock); > } > > +static int gen11_service_shared_iir(struct drm_i915_private *dev_priv, > + const unsigned int bank, > + const unsigned int bit) > +{ > + u64 wait_end; > + u32 ident; > + int irq; > + > + I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); > + /* > + * NB: Specs do not specify how long to spin wait. > + * Taking 100us as an educated guess > + */ > + wait_end = (local_clock() >> 10) + 100; > + do { > + ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank)); > + } while (!(ident & GEN11_INTR_DATA_VALID) && > + !time_after32(local_clock() >> 10, wait_end)); Now you are just mixing types willy nilly :) No need for wait_end to be 64b when we are looking at a 100 interval. > + > + if (!(ident & GEN11_INTR_DATA_VALID)) { > + DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit); > + return -ETIMEDOUT; > + } > + > + irq = ident & GEN11_INTR_ENGINE_MASK; > + > + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident); > + > + return irq; return ident & GEN11_INTR_ENGINE_MASK; no need for irq, and why int return type? Why is this gen11 specific helper so far away from the irq_handler? > +static __always_inline void > +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir) > +{ > + gen8_cs_irq_handler(engine, iir, 0); > +} > + > +static void > +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, const u32 master_ctl) > +{ > + u16 irq[2][32]; > + unsigned int bank, engine; > + > + memset(irq, 0, sizeof(irq)); > + > + for (bank = 0; bank < 2; bank++) { > + unsigned long tmp; > + unsigned int bit; > + u32 dw; > + int ret; > + > + if (!(master_ctl & GEN11_GT_DW_IRQ(bank))) > + continue; > + > + dw = I915_READ_FW(GEN11_GT_INTR_DW(bank)); > + if (!dw) > + DRM_ERROR("GT_INTR_DW%u blank!\n", bank); > + > + tmp = dw; > + for_each_set_bit(bit, &tmp, 32) { tmp is not required here. > + ret = gen11_service_shared_iir(dev_priv, bank, bit); > + if (unlikely(ret < 0)) > + continue; > + > + irq[bank][bit] = ret; > + } > + > + I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw); If we process the banks here, we won't need to memset 128 bytes and scan untouched cachelines! > + } > + > + if (irq[0][GEN11_RCS0]) > + gen11_cs_irq_handler(dev_priv->engine[RCS], > + irq[0][GEN11_RCS0]); > + > + if (irq[0][GEN11_BCS]) > + gen11_cs_irq_handler(dev_priv->engine[BCS], > + irq[0][GEN11_BCS]); > + > + for (engine = 0; engine < I915_MAX_VCS; engine++) > + if (irq[1][GEN11_VCS(engine)]) > + gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)], > + irq[1][GEN11_VCS(engine)]); > + > + for (engine = 0; engine < I915_MAX_VECS; engine++) > + if (irq[1][GEN11_VECS(engine)]) > + gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)], > + irq[1][GEN11_VECS(engine)]); Keep reminding yourself that this is the hottest function in the entire i915.ko. > +} > + > +static irqreturn_t gen11_irq_handler(int irq, void *arg) > +{ > + struct drm_device *dev = arg; > + struct drm_i915_private *dev_priv = dev->dev_private; What? > + u32 master_ctl; > + u32 disp_ctl; Why is this at top level scope? > + if (!intel_irqs_enabled(dev_priv)) > + return IRQ_NONE; > + > + master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ); > + master_ctl &= ~GEN11_MASTER_IRQ; > + if (!master_ctl) > + return IRQ_NONE; > + > + /* Disable interrupts. */ > + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0); > + > + /* IRQs are synced during runtime_suspend, we don't require a wakeref */ > + disable_rpm_wakeref_asserts(dev_priv); > + > + /* Find, clear, then process each source of interrupt. */ > + gen11_gt_irq_handler(dev_priv, master_ctl); > + > + if (master_ctl & GEN11_DISPLAY_IRQ) { > + disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL); > + gen8_de_irq_handler(dev_priv, disp_ctl); > + } > + > + /* Acknowledge and enable interrupts. */ > + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl); > + POSTING_READ_FW(GEN11_GFX_MSTR_IRQ); > + > + enable_rpm_wakeref_asserts(dev_priv); What happened to the onion? gen8 is broken as well, sure I sent patches to fix that. The posting read is ott, and you don't need to disable the asserts around the GT irq handler. -Chris
Chris Wilson <chris@chris-wilson.co.uk> writes: > Quoting Mika Kuoppala (2018-02-14 14:12:13) >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> v2: Rebase. >> >> v3: >> * Remove DPF, it has been removed from SKL+. >> * Fix -internal rebase wrt. execlists interrupt handling. >> >> v4: Rebase. >> >> v5: >> * Updated for POR changes. (Daniele Ceraolo Spurio) >> * Merged with irq handling fixes by Daniele Ceraolo Spurio: >> * Simplify the code by using gen8_cs_irq_handler. >> * Fix interrupt handling for the upstream kernel. >> >> v6: >> * Remove early bringup debug messages (Tvrtko) >> * Add NB about arbitrary spin wait timeout (Tvrtko) >> >> v7 (from Paulo): >> * Don't try to write RO bits to registers. >> * Don't check for PCH types that don't exist. PCH interrupts are not >> here yet. >> >> v9: >> * squashed in selector and shared register handling (Daniele) >> * skip writing of irq if data is not valid (Daniele) >> * use time_after32 (Chris) >> * use I915_MAX_VCS and I915_MAX_VECS (Daniele) >> * remove fake pm interrupt handling for later patch (Mika) >> >> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Cc: Chris Wilson <chris@chris-wilson.co.uk> >> Cc: Oscar Mateo <oscar.mateo@intel.com> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> >> Signed-off-by: Oscar Mateo <oscar.mateo@intel.com> >> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> >> --- >> drivers/gpu/drm/i915/i915_irq.c | 212 ++++++++++++++++++++++++++++++++++++++++ >> drivers/gpu/drm/i915/intel_pm.c | 7 +- >> 2 files changed, 218 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c >> index b886bd459acc..9a2d12c8c44c 100644 >> --- a/drivers/gpu/drm/i915/i915_irq.c >> +++ b/drivers/gpu/drm/i915/i915_irq.c >> @@ -408,6 +408,37 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) >> spin_unlock_irq(&dev_priv->irq_lock); >> } >> >> +static int gen11_service_shared_iir(struct drm_i915_private *dev_priv, >> + const unsigned int bank, >> + const unsigned int bit) >> +{ >> + u64 wait_end; >> + u32 ident; >> + int irq; >> + >> + I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); >> + /* >> + * NB: Specs do not specify how long to spin wait. >> + * Taking 100us as an educated guess >> + */ >> + wait_end = (local_clock() >> 10) + 100; >> + do { >> + ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank)); >> + } while (!(ident & GEN11_INTR_DATA_VALID) && >> + !time_after32(local_clock() >> 10, wait_end)); > > Now you are just mixing types willy nilly :) > > No need for wait_end to be 64b when we are looking at a 100 interval. I threw the poll away. We can add it later if someone objects and/or evidence indicates that it is needed. But polling for 100us just in case in irq handler should not be the first step. > >> + >> + if (!(ident & GEN11_INTR_DATA_VALID)) { >> + DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit); >> + return -ETIMEDOUT; >> + } >> + >> + irq = ident & GEN11_INTR_ENGINE_MASK; >> + >> + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident); Bspec tells that valid bit write should be enough here. >> + >> + return irq; > > return ident & GEN11_INTR_ENGINE_MASK; > > no need for irq, and why int return type? I made it return zero on unvalid. > > Why is this gen11 specific helper so far away from the irq_handler? Due to later patch in this series needing it, rc6 enabling due to rps reset. I moved those closer in both patches. > >> +static __always_inline void >> +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir) >> +{ >> + gen8_cs_irq_handler(engine, iir, 0); >> +} >> + >> +static void >> +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, const u32 master_ctl) >> +{ >> + u16 irq[2][32]; >> + unsigned int bank, engine; >> + >> + memset(irq, 0, sizeof(irq)); >> + >> + for (bank = 0; bank < 2; bank++) { >> + unsigned long tmp; >> + unsigned int bit; >> + u32 dw; >> + int ret; >> + >> + if (!(master_ctl & GEN11_GT_DW_IRQ(bank))) >> + continue; >> + >> + dw = I915_READ_FW(GEN11_GT_INTR_DW(bank)); >> + if (!dw) >> + DRM_ERROR("GT_INTR_DW%u blank!\n", bank); >> + >> + tmp = dw; >> + for_each_set_bit(bit, &tmp, 32) { > > tmp is not required here. reading directly now to unsigned long dw_intr. > >> + ret = gen11_service_shared_iir(dev_priv, bank, bit); >> + if (unlikely(ret < 0)) >> + continue; >> + >> + irq[bank][bit] = ret; >> + } >> + >> + I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw); > > If we process the banks here, we won't need to memset 128 bytes and scan > untouched cachelines! Made it so. Bspec says that we need to serve the engine shared irq before clearing the corresponding bank bit. I avoided trickery and kept it so that we minimize writes by clearing them all. > >> + } >> + >> + if (irq[0][GEN11_RCS0]) >> + gen11_cs_irq_handler(dev_priv->engine[RCS], >> + irq[0][GEN11_RCS0]); >> + >> + if (irq[0][GEN11_BCS]) >> + gen11_cs_irq_handler(dev_priv->engine[BCS], >> + irq[0][GEN11_BCS]); >> + >> + for (engine = 0; engine < I915_MAX_VCS; engine++) >> + if (irq[1][GEN11_VCS(engine)]) >> + gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)], >> + irq[1][GEN11_VCS(engine)]); >> + >> + for (engine = 0; engine < I915_MAX_VECS; engine++) >> + if (irq[1][GEN11_VECS(engine)]) >> + gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)], >> + irq[1][GEN11_VECS(engine)]); > > Keep reminding yourself that this is the hottest function in the entire > i915.ko. The serving of engine specific irq is now done using outer and inner switches. Atleast it looks leaner :O > >> +} >> + >> +static irqreturn_t gen11_irq_handler(int irq, void *arg) >> +{ >> + struct drm_device *dev = arg; >> + struct drm_i915_private *dev_priv = dev->dev_private; > > What? struct drm_i915_private * const dev_priv = to_i915((struct drm_device *)arg); > >> + u32 master_ctl; >> + u32 disp_ctl; > > Why is this at top level scope? It is no more at all. > >> + if (!intel_irqs_enabled(dev_priv)) >> + return IRQ_NONE; >> + >> + master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ); >> + master_ctl &= ~GEN11_MASTER_IRQ; >> + if (!master_ctl) >> + return IRQ_NONE; >> + >> + /* Disable interrupts. */ >> + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0); >> + >> + /* IRQs are synced during runtime_suspend, we don't require a wakeref */ >> + disable_rpm_wakeref_asserts(dev_priv); >> + >> + /* Find, clear, then process each source of interrupt. */ >> + gen11_gt_irq_handler(dev_priv, master_ctl); >> + >> + if (master_ctl & GEN11_DISPLAY_IRQ) { >> + disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL); >> + gen8_de_irq_handler(dev_priv, disp_ctl); >> + } >> + >> + /* Acknowledge and enable interrupts. */ >> + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl); >> + POSTING_READ_FW(GEN11_GFX_MSTR_IRQ); >> + >> + enable_rpm_wakeref_asserts(dev_priv); > > What happened to the onion? gen8 is broken as well, sure I sent patches > to fix that. The posting read is ott, and you don't need to disable the > asserts around the GT irq handler. I moved the asserts inside display scope, like in gen8 version. Thanks for comments, -Mika
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index b886bd459acc..9a2d12c8c44c 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -408,6 +408,37 @@ void gen6_reset_rps_interrupts(struct drm_i915_private *dev_priv) spin_unlock_irq(&dev_priv->irq_lock); } +static int gen11_service_shared_iir(struct drm_i915_private *dev_priv, + const unsigned int bank, + const unsigned int bit) +{ + u64 wait_end; + u32 ident; + int irq; + + I915_WRITE_FW(GEN11_IIR_REG_SELECTOR(bank), BIT(bit)); + /* + * NB: Specs do not specify how long to spin wait. + * Taking 100us as an educated guess + */ + wait_end = (local_clock() >> 10) + 100; + do { + ident = I915_READ_FW(GEN11_INTR_IDENTITY_REG(bank)); + } while (!(ident & GEN11_INTR_DATA_VALID) && + !time_after32(local_clock() >> 10, wait_end)); + + if (!(ident & GEN11_INTR_DATA_VALID)) { + DRM_ERROR("INTR_IDENTITY_REG%u:%u timed out!\n", bank, bit); + return -ETIMEDOUT; + } + + irq = ident & GEN11_INTR_ENGINE_MASK; + + I915_WRITE_FW(GEN11_INTR_IDENTITY_REG(bank), ident); + + return irq; +} + void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; @@ -415,6 +446,9 @@ void gen6_enable_rps_interrupts(struct drm_i915_private *dev_priv) if (READ_ONCE(rps->interrupts_enabled)) return; + if (WARN_ON_ONCE(IS_GEN11(dev_priv))) + return; + spin_lock_irq(&dev_priv->irq_lock); WARN_ON_ONCE(rps->pm_iir); WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); @@ -431,6 +465,9 @@ void gen6_disable_rps_interrupts(struct drm_i915_private *dev_priv) if (!READ_ONCE(rps->interrupts_enabled)) return; + if (WARN_ON_ONCE(IS_GEN11(dev_priv))) + return; + spin_lock_irq(&dev_priv->irq_lock); rps->interrupts_enabled = false; @@ -2746,6 +2783,102 @@ static void __fini_wedge(struct wedge_me *w) (W)->i915; \ __fini_wedge((W))) +static __always_inline void +gen11_cs_irq_handler(struct intel_engine_cs *engine, u32 iir) +{ + gen8_cs_irq_handler(engine, iir, 0); +} + +static void +gen11_gt_irq_handler(struct drm_i915_private *dev_priv, const u32 master_ctl) +{ + u16 irq[2][32]; + unsigned int bank, engine; + + memset(irq, 0, sizeof(irq)); + + for (bank = 0; bank < 2; bank++) { + unsigned long tmp; + unsigned int bit; + u32 dw; + int ret; + + if (!(master_ctl & GEN11_GT_DW_IRQ(bank))) + continue; + + dw = I915_READ_FW(GEN11_GT_INTR_DW(bank)); + if (!dw) + DRM_ERROR("GT_INTR_DW%u blank!\n", bank); + + tmp = dw; + for_each_set_bit(bit, &tmp, 32) { + ret = gen11_service_shared_iir(dev_priv, bank, bit); + if (unlikely(ret < 0)) + continue; + + irq[bank][bit] = ret; + } + + I915_WRITE_FW(GEN11_GT_INTR_DW(bank), dw); + } + + if (irq[0][GEN11_RCS0]) + gen11_cs_irq_handler(dev_priv->engine[RCS], + irq[0][GEN11_RCS0]); + + if (irq[0][GEN11_BCS]) + gen11_cs_irq_handler(dev_priv->engine[BCS], + irq[0][GEN11_BCS]); + + for (engine = 0; engine < I915_MAX_VCS; engine++) + if (irq[1][GEN11_VCS(engine)]) + gen11_cs_irq_handler(dev_priv->engine[_VCS(engine)], + irq[1][GEN11_VCS(engine)]); + + for (engine = 0; engine < I915_MAX_VECS; engine++) + if (irq[1][GEN11_VECS(engine)]) + gen11_cs_irq_handler(dev_priv->engine[_VECS(engine)], + irq[1][GEN11_VECS(engine)]); +} + +static irqreturn_t gen11_irq_handler(int irq, void *arg) +{ + struct drm_device *dev = arg; + struct drm_i915_private *dev_priv = dev->dev_private; + u32 master_ctl; + u32 disp_ctl; + + if (!intel_irqs_enabled(dev_priv)) + return IRQ_NONE; + + master_ctl = I915_READ_FW(GEN11_GFX_MSTR_IRQ); + master_ctl &= ~GEN11_MASTER_IRQ; + if (!master_ctl) + return IRQ_NONE; + + /* Disable interrupts. */ + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, 0); + + /* IRQs are synced during runtime_suspend, we don't require a wakeref */ + disable_rpm_wakeref_asserts(dev_priv); + + /* Find, clear, then process each source of interrupt. */ + gen11_gt_irq_handler(dev_priv, master_ctl); + + if (master_ctl & GEN11_DISPLAY_IRQ) { + disp_ctl = I915_READ_FW(GEN11_DISPLAY_INT_CTL); + gen8_de_irq_handler(dev_priv, disp_ctl); + } + + /* Acknowledge and enable interrupts. */ + I915_WRITE_FW(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ | master_ctl); + POSTING_READ_FW(GEN11_GFX_MSTR_IRQ); + + enable_rpm_wakeref_asserts(dev_priv); + + return IRQ_HANDLED; +} + /** * i915_reset_device - do process context error handling work * @dev_priv: i915 device private @@ -3159,6 +3292,42 @@ static void gen8_irq_reset(struct drm_device *dev) ibx_irq_reset(dev_priv); } +static void gen11_gt_irq_reset(struct drm_i915_private *dev_priv) +{ + /* Disable RCS, BCS, VCS and VECS class engines. */ + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, 0); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, 0); + + /* Restore masks irqs on RCS, BCS, VCS and VECS engines. */ + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~0); + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~0); + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~0); + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~0); + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~0); +} + +static void gen11_irq_reset(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + int pipe; + + I915_WRITE(GEN11_GFX_MSTR_IRQ, 0); + POSTING_READ(GEN11_GFX_MSTR_IRQ); + + gen11_gt_irq_reset(dev_priv); + + I915_WRITE(GEN11_DISPLAY_INT_CTL, 0); + + for_each_pipe(dev_priv, pipe) + if (intel_display_power_is_enabled(dev_priv, + POWER_DOMAIN_PIPE(pipe))) + GEN8_IRQ_RESET_NDX(DE_PIPE, pipe); + + GEN3_IRQ_RESET(GEN8_DE_PORT_); + GEN3_IRQ_RESET(GEN8_DE_MISC_); + GEN3_IRQ_RESET(GEN8_PCU_); +} + void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv, u8 pipe_mask) { @@ -3656,6 +3825,41 @@ static int gen8_irq_postinstall(struct drm_device *dev) return 0; } +static void gen11_gt_irq_postinstall(struct drm_i915_private *dev_priv) +{ + const u32 irqs = GT_RENDER_USER_INTERRUPT | GT_CONTEXT_SWITCH_INTERRUPT; + + BUILD_BUG_ON(irqs & 0xffff0000); + + /* Enable RCS, BCS, VCS and VECS class interrupts. */ + I915_WRITE(GEN11_RENDER_COPY_INTR_ENABLE, irqs << 16 | irqs); + I915_WRITE(GEN11_VCS_VECS_INTR_ENABLE, irqs << 16 | irqs); + + /* Unmask irqs on RCS, BCS, VCS and VECS engines. */ + I915_WRITE(GEN11_RCS0_RSVD_INTR_MASK, ~(irqs << 16)); + I915_WRITE(GEN11_BCS_RSVD_INTR_MASK, ~(irqs << 16)); + I915_WRITE(GEN11_VCS0_VCS1_INTR_MASK, ~(irqs | irqs << 16)); + I915_WRITE(GEN11_VCS2_VCS3_INTR_MASK, ~(irqs | irqs << 16)); + I915_WRITE(GEN11_VECS0_VECS1_INTR_MASK, ~(irqs | irqs << 16)); + + dev_priv->pm_imr = 0xffffffff; /* TODO */ +} + +static int gen11_irq_postinstall(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + + gen11_gt_irq_postinstall(dev_priv); + gen8_de_irq_postinstall(dev_priv); + + I915_WRITE(GEN11_DISPLAY_INT_CTL, GEN11_DISPLAY_IRQ_ENABLE); + + I915_WRITE(GEN11_GFX_MSTR_IRQ, GEN11_MASTER_IRQ); + POSTING_READ(GEN11_GFX_MSTR_IRQ); + + return 0; +} + static int cherryview_irq_postinstall(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -4104,6 +4308,14 @@ void intel_irq_init(struct drm_i915_private *dev_priv) dev->driver->enable_vblank = i965_enable_vblank; dev->driver->disable_vblank = i965_disable_vblank; dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup; + } else if (INTEL_GEN(dev_priv) >= 11) { + dev->driver->irq_handler = gen11_irq_handler; + dev->driver->irq_preinstall = gen11_irq_reset; + dev->driver->irq_postinstall = gen11_irq_postinstall; + dev->driver->irq_uninstall = gen11_irq_reset; + dev->driver->enable_vblank = gen8_enable_vblank; + dev->driver->disable_vblank = gen8_disable_vblank; + dev_priv->display.hpd_irq_setup = spt_hpd_irq_setup; } else if (INTEL_GEN(dev_priv) >= 8) { dev->driver->irq_handler = gen8_irq_handler; dev->driver->irq_preinstall = gen8_irq_reset; diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 98d336a1d885..e207c3a2eea9 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -8027,7 +8027,10 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) dev_priv->gt_pm.rc6.enabled = true; /* force RC6 disabling */ intel_disable_gt_powersave(dev_priv); - gen6_reset_rps_interrupts(dev_priv); + if (INTEL_GEN(dev_priv) < 11) + gen6_reset_rps_interrupts(dev_priv); + else + WARN_ON_ONCE(1); } static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) @@ -8140,6 +8143,8 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv) cherryview_enable_rps(dev_priv); } else if (IS_VALLEYVIEW(dev_priv)) { valleyview_enable_rps(dev_priv); + } else if (WARN_ON_ONCE(INTEL_GEN(dev_priv) >= 11)) { + /* TODO */ } else if (INTEL_GEN(dev_priv) >= 9) { gen9_enable_rps(dev_priv); } else if (IS_BROADWELL(dev_priv)) {