| Message ID | 20180220153755.13509-2-mika.kuoppala@linux.intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 20/02/18 07:37, Mika Kuoppala wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Show GEN11 specific interrupt registers in debugfs > > v2: Update for POR changes. (Daniele Ceraolo Spurio) > v3: get runtime pm ref. unify common parts with gen8 (Daniele) > > Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com> > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> > --- > drivers/gpu/drm/i915/i915_debugfs.c | 139 ++++++++++++++++++++++++------------ > 1 file changed, 95 insertions(+), 44 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c > index 05b41045b8f9..d4991b335cf5 100644 > --- a/drivers/gpu/drm/i915/i915_debugfs.c > +++ b/drivers/gpu/drm/i915/i915_debugfs.c > @@ -646,6 +646,56 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data) > return 0; > } > > +static void gen8_display_interrupt_info(struct seq_file *m) > +{ > + struct drm_i915_private *dev_priv = node_to_i915(m->private); > + int pipe; > + > + for_each_pipe(dev_priv, pipe) { > + enum intel_display_power_domain power_domain; > + > + power_domain = POWER_DOMAIN_PIPE(pipe); > + if (!intel_display_power_get_if_enabled(dev_priv, > + power_domain)) { > + seq_printf(m, "Pipe %c power disabled\n", > + pipe_name(pipe)); > + continue; > + } > + seq_printf(m, "Pipe %c IMR:\t%08x\n", > + pipe_name(pipe), > + I915_READ(GEN8_DE_PIPE_IMR(pipe))); > + seq_printf(m, "Pipe %c IIR:\t%08x\n", > + pipe_name(pipe), > + I915_READ(GEN8_DE_PIPE_IIR(pipe))); > + seq_printf(m, "Pipe %c IER:\t%08x\n", > + pipe_name(pipe), > + I915_READ(GEN8_DE_PIPE_IER(pipe))); > + > + intel_display_power_put(dev_priv, power_domain); > + } > + > + seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", > + I915_READ(GEN8_DE_PORT_IMR)); > + seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", > + I915_READ(GEN8_DE_PORT_IIR)); > + seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", > + I915_READ(GEN8_DE_PORT_IER)); > + > + seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", > + I915_READ(GEN8_DE_MISC_IMR)); > + seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", > + I915_READ(GEN8_DE_MISC_IIR)); > + seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", > + I915_READ(GEN8_DE_MISC_IER)); > + > + seq_printf(m, "PCU interrupt mask:\t%08x\n", > + I915_READ(GEN8_PCU_IMR)); > + seq_printf(m, "PCU interrupt identity:\t%08x\n", > + I915_READ(GEN8_PCU_IIR)); > + seq_printf(m, "PCU interrupt enable:\t%08x\n", > + I915_READ(GEN8_PCU_IER)); > +} > + > static int i915_interrupt_info(struct seq_file *m, void *data) > { > struct drm_i915_private *dev_priv = node_to_i915(m->private); > @@ -709,6 +759,27 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > I915_READ(GEN8_PCU_IIR)); > seq_printf(m, "PCU interrupt enable:\t%08x\n", > I915_READ(GEN8_PCU_IER)); > + } else if (INTEL_GEN(dev_priv) >= 11) { > + seq_printf(m, "Master Interrupt Control: %08x\n", > + I915_READ(GEN11_GFX_MSTR_IRQ)); > + > + seq_printf(m, "Render/Copy Intr Enable: %08x\n", > + I915_READ(GEN11_RENDER_COPY_INTR_ENABLE)); > + seq_printf(m, "VCS/VECS Intr Enable: %08x\n", > + I915_READ(GEN11_VCS_VECS_INTR_ENABLE)); > + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", > + I915_READ(GEN11_GUC_SG_INTR_ENABLE)); > + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", > + I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE)); > + seq_printf(m, "Crypto Intr Enable:\t %08x\n", > + I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE)); > + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", > + I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE)); > + > + seq_printf(m, "Display Interrupt Control:\t%08x\n", > + I915_READ(GEN11_DISPLAY_INT_CTL)); > + > + gen8_display_interrupt_info(m); > } else if (INTEL_GEN(dev_priv) >= 8) { > seq_printf(m, "Master Interrupt Control:\t%08x\n", > I915_READ(GEN8_MASTER_IRQ)); > @@ -722,49 +793,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > i, I915_READ(GEN8_GT_IER(i))); > } > > - for_each_pipe(dev_priv, pipe) { > - enum intel_display_power_domain power_domain; > - > - power_domain = POWER_DOMAIN_PIPE(pipe); > - if (!intel_display_power_get_if_enabled(dev_priv, > - power_domain)) { > - seq_printf(m, "Pipe %c power disabled\n", > - pipe_name(pipe)); > - continue; > - } > - seq_printf(m, "Pipe %c IMR:\t%08x\n", > - pipe_name(pipe), > - I915_READ(GEN8_DE_PIPE_IMR(pipe))); > - seq_printf(m, "Pipe %c IIR:\t%08x\n", > - pipe_name(pipe), > - I915_READ(GEN8_DE_PIPE_IIR(pipe))); > - seq_printf(m, "Pipe %c IER:\t%08x\n", > - pipe_name(pipe), > - I915_READ(GEN8_DE_PIPE_IER(pipe))); > - > - intel_display_power_put(dev_priv, power_domain); > - } > - > - seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", > - I915_READ(GEN8_DE_PORT_IMR)); > - seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", > - I915_READ(GEN8_DE_PORT_IIR)); > - seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", > - I915_READ(GEN8_DE_PORT_IER)); > - > - seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", > - I915_READ(GEN8_DE_MISC_IMR)); > - seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", > - I915_READ(GEN8_DE_MISC_IIR)); > - seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", > - I915_READ(GEN8_DE_MISC_IER)); > - > - seq_printf(m, "PCU interrupt mask:\t%08x\n", > - I915_READ(GEN8_PCU_IMR)); > - seq_printf(m, "PCU interrupt identity:\t%08x\n", > - I915_READ(GEN8_PCU_IIR)); > - seq_printf(m, "PCU interrupt enable:\t%08x\n", > - I915_READ(GEN8_PCU_IER)); > + gen8_display_interrupt_info(m); > } else if (IS_VALLEYVIEW(dev_priv)) { > seq_printf(m, "Display IER:\t%08x\n", > I915_READ(VLV_IER)); > @@ -846,13 +875,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data) > seq_printf(m, "Graphics Interrupt mask: %08x\n", > I915_READ(GTIMR)); > } > - if (INTEL_GEN(dev_priv) >= 6) { > + > + if (INTEL_GEN(dev_priv) >= 11) { > + seq_printf(m, "RCS Intr Mask:\t %08x\n", > + I915_READ(GEN11_RCS0_RSVD_INTR_MASK)); > + seq_printf(m, "BCS Intr Mask:\t %08x\n", > + I915_READ(GEN11_BCS_RSVD_INTR_MASK)); > + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", > + I915_READ(GEN11_VCS0_VCS1_INTR_MASK)); > + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", > + I915_READ(GEN11_VCS2_VCS3_INTR_MASK)); > + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", > + I915_READ(GEN11_VECS0_VECS1_INTR_MASK)); > + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", > + I915_READ(GEN11_GUC_SG_INTR_MASK)); > + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", > + I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK)); > + seq_printf(m, "Crypto Intr Mask:\t %08x\n", > + I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK)); > + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", > + I915_READ(GEN11_GUNIT_CSME_INTR_MASK)); > + > + } else if (INTEL_GEN(dev_priv) >= 6) { > for_each_engine(engine, dev_priv, id) { > seq_printf(m, > "Graphics Interrupt mask (%s): %08x\n", > engine->name, I915_READ_IMR(engine)); > } > } > + > intel_runtime_pm_put(dev_priv); > > return 0; >
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> writes: > On 20/02/18 07:37, Mika Kuoppala wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> Show GEN11 specific interrupt registers in debugfs >> >> v2: Update for POR changes. (Daniele Ceraolo Spurio) >> v3: get runtime pm ref. unify common parts with gen8 (Daniele) >> >> Cc: Ceraolo Spurio, Daniele <daniele.ceraolospurio@intel.com> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> >> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com> > > Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com> Pushed 1/4 and this one. Thank you for patches and review. -Mika
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 05b41045b8f9..d4991b335cf5 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -646,6 +646,56 @@ static int i915_gem_batch_pool_info(struct seq_file *m, void *data) return 0; } +static void gen8_display_interrupt_info(struct seq_file *m) +{ + struct drm_i915_private *dev_priv = node_to_i915(m->private); + int pipe; + + for_each_pipe(dev_priv, pipe) { + enum intel_display_power_domain power_domain; + + power_domain = POWER_DOMAIN_PIPE(pipe); + if (!intel_display_power_get_if_enabled(dev_priv, + power_domain)) { + seq_printf(m, "Pipe %c power disabled\n", + pipe_name(pipe)); + continue; + } + seq_printf(m, "Pipe %c IMR:\t%08x\n", + pipe_name(pipe), + I915_READ(GEN8_DE_PIPE_IMR(pipe))); + seq_printf(m, "Pipe %c IIR:\t%08x\n", + pipe_name(pipe), + I915_READ(GEN8_DE_PIPE_IIR(pipe))); + seq_printf(m, "Pipe %c IER:\t%08x\n", + pipe_name(pipe), + I915_READ(GEN8_DE_PIPE_IER(pipe))); + + intel_display_power_put(dev_priv, power_domain); + } + + seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", + I915_READ(GEN8_DE_PORT_IMR)); + seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", + I915_READ(GEN8_DE_PORT_IIR)); + seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", + I915_READ(GEN8_DE_PORT_IER)); + + seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", + I915_READ(GEN8_DE_MISC_IMR)); + seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", + I915_READ(GEN8_DE_MISC_IIR)); + seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", + I915_READ(GEN8_DE_MISC_IER)); + + seq_printf(m, "PCU interrupt mask:\t%08x\n", + I915_READ(GEN8_PCU_IMR)); + seq_printf(m, "PCU interrupt identity:\t%08x\n", + I915_READ(GEN8_PCU_IIR)); + seq_printf(m, "PCU interrupt enable:\t%08x\n", + I915_READ(GEN8_PCU_IER)); +} + static int i915_interrupt_info(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -709,6 +759,27 @@ static int i915_interrupt_info(struct seq_file *m, void *data) I915_READ(GEN8_PCU_IIR)); seq_printf(m, "PCU interrupt enable:\t%08x\n", I915_READ(GEN8_PCU_IER)); + } else if (INTEL_GEN(dev_priv) >= 11) { + seq_printf(m, "Master Interrupt Control: %08x\n", + I915_READ(GEN11_GFX_MSTR_IRQ)); + + seq_printf(m, "Render/Copy Intr Enable: %08x\n", + I915_READ(GEN11_RENDER_COPY_INTR_ENABLE)); + seq_printf(m, "VCS/VECS Intr Enable: %08x\n", + I915_READ(GEN11_VCS_VECS_INTR_ENABLE)); + seq_printf(m, "GUC/SG Intr Enable:\t %08x\n", + I915_READ(GEN11_GUC_SG_INTR_ENABLE)); + seq_printf(m, "GPM/WGBOXPERF Intr Enable: %08x\n", + I915_READ(GEN11_GPM_WGBOXPERF_INTR_ENABLE)); + seq_printf(m, "Crypto Intr Enable:\t %08x\n", + I915_READ(GEN11_CRYPTO_RSVD_INTR_ENABLE)); + seq_printf(m, "GUnit/CSME Intr Enable:\t %08x\n", + I915_READ(GEN11_GUNIT_CSME_INTR_ENABLE)); + + seq_printf(m, "Display Interrupt Control:\t%08x\n", + I915_READ(GEN11_DISPLAY_INT_CTL)); + + gen8_display_interrupt_info(m); } else if (INTEL_GEN(dev_priv) >= 8) { seq_printf(m, "Master Interrupt Control:\t%08x\n", I915_READ(GEN8_MASTER_IRQ)); @@ -722,49 +793,7 @@ static int i915_interrupt_info(struct seq_file *m, void *data) i, I915_READ(GEN8_GT_IER(i))); } - for_each_pipe(dev_priv, pipe) { - enum intel_display_power_domain power_domain; - - power_domain = POWER_DOMAIN_PIPE(pipe); - if (!intel_display_power_get_if_enabled(dev_priv, - power_domain)) { - seq_printf(m, "Pipe %c power disabled\n", - pipe_name(pipe)); - continue; - } - seq_printf(m, "Pipe %c IMR:\t%08x\n", - pipe_name(pipe), - I915_READ(GEN8_DE_PIPE_IMR(pipe))); - seq_printf(m, "Pipe %c IIR:\t%08x\n", - pipe_name(pipe), - I915_READ(GEN8_DE_PIPE_IIR(pipe))); - seq_printf(m, "Pipe %c IER:\t%08x\n", - pipe_name(pipe), - I915_READ(GEN8_DE_PIPE_IER(pipe))); - - intel_display_power_put(dev_priv, power_domain); - } - - seq_printf(m, "Display Engine port interrupt mask:\t%08x\n", - I915_READ(GEN8_DE_PORT_IMR)); - seq_printf(m, "Display Engine port interrupt identity:\t%08x\n", - I915_READ(GEN8_DE_PORT_IIR)); - seq_printf(m, "Display Engine port interrupt enable:\t%08x\n", - I915_READ(GEN8_DE_PORT_IER)); - - seq_printf(m, "Display Engine misc interrupt mask:\t%08x\n", - I915_READ(GEN8_DE_MISC_IMR)); - seq_printf(m, "Display Engine misc interrupt identity:\t%08x\n", - I915_READ(GEN8_DE_MISC_IIR)); - seq_printf(m, "Display Engine misc interrupt enable:\t%08x\n", - I915_READ(GEN8_DE_MISC_IER)); - - seq_printf(m, "PCU interrupt mask:\t%08x\n", - I915_READ(GEN8_PCU_IMR)); - seq_printf(m, "PCU interrupt identity:\t%08x\n", - I915_READ(GEN8_PCU_IIR)); - seq_printf(m, "PCU interrupt enable:\t%08x\n", - I915_READ(GEN8_PCU_IER)); + gen8_display_interrupt_info(m); } else if (IS_VALLEYVIEW(dev_priv)) { seq_printf(m, "Display IER:\t%08x\n", I915_READ(VLV_IER)); @@ -846,13 +875,35 @@ static int i915_interrupt_info(struct seq_file *m, void *data) seq_printf(m, "Graphics Interrupt mask: %08x\n", I915_READ(GTIMR)); } - if (INTEL_GEN(dev_priv) >= 6) { + + if (INTEL_GEN(dev_priv) >= 11) { + seq_printf(m, "RCS Intr Mask:\t %08x\n", + I915_READ(GEN11_RCS0_RSVD_INTR_MASK)); + seq_printf(m, "BCS Intr Mask:\t %08x\n", + I915_READ(GEN11_BCS_RSVD_INTR_MASK)); + seq_printf(m, "VCS0/VCS1 Intr Mask:\t %08x\n", + I915_READ(GEN11_VCS0_VCS1_INTR_MASK)); + seq_printf(m, "VCS2/VCS3 Intr Mask:\t %08x\n", + I915_READ(GEN11_VCS2_VCS3_INTR_MASK)); + seq_printf(m, "VECS0/VECS1 Intr Mask:\t %08x\n", + I915_READ(GEN11_VECS0_VECS1_INTR_MASK)); + seq_printf(m, "GUC/SG Intr Mask:\t %08x\n", + I915_READ(GEN11_GUC_SG_INTR_MASK)); + seq_printf(m, "GPM/WGBOXPERF Intr Mask: %08x\n", + I915_READ(GEN11_GPM_WGBOXPERF_INTR_MASK)); + seq_printf(m, "Crypto Intr Mask:\t %08x\n", + I915_READ(GEN11_CRYPTO_RSVD_INTR_MASK)); + seq_printf(m, "Gunit/CSME Intr Mask:\t %08x\n", + I915_READ(GEN11_GUNIT_CSME_INTR_MASK)); + + } else if (INTEL_GEN(dev_priv) >= 6) { for_each_engine(engine, dev_priv, id) { seq_printf(m, "Graphics Interrupt mask (%s): %08x\n", engine->name, I915_READ_IMR(engine)); } } + intel_runtime_pm_put(dev_priv); return 0;