From patchwork Thu Feb 22 09:05:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10234895 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6584D60349 for ; Thu, 22 Feb 2018 09:05:28 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 65E7628A46 for ; Thu, 22 Feb 2018 09:05:28 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5732728A72; Thu, 22 Feb 2018 09:05:28 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7084A28A46 for ; Thu, 22 Feb 2018 09:05:27 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 493926EC7A; Thu, 22 Feb 2018 09:05:26 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id D344C6EC7A for ; Thu, 22 Feb 2018 09:05:24 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id q83so2441504wme.5 for ; Thu, 22 Feb 2018 01:05:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Um6ICLniEYKqmvgKtr24f3hDlj5CekoQt1tKw6JDW1U=; b=chyogSR3Rk9UKqfUM3W4jHb6FN/ZjKBHDrxIofERPfnf4J7v1eq12zWa3ptHtlJrh/ Of5RHepL07BwaqGxai3nt/8h6jkBz2QZ8OqEXgO3h1mbU0taZcebPPwBaQqeEgHk+x7X Qn71klzwz4JUwWvi/5yz7JNF+4kL7qdB3x5+8X5Aw/RAUXEjrfsXy+odh1YpaJo6/vvC V6EYd+JL5Rpt7wfkmmsEyPqawOv2a/LeU7prYjiZz/DglyinODedOBEwwsOYRGTUfM59 0rQOpji2dEndxFgqz9cuNXG/OTFj0W/mh7dVJ1hFW9vk6526C0W4HvTj3jahn3uZdPIN dEsQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Um6ICLniEYKqmvgKtr24f3hDlj5CekoQt1tKw6JDW1U=; b=Mc3MReBGP2hhPHAVClgTWNTmuFs5RUiTIGe0Ee5epydEN6a52qeBVtr4pydrOh5ZA1 MmzuESKCfq4ziTz5k3W1+FcNcDG/IgjcTDSEqNqA3DycBEFQ3uk/ofJRgrGdiVWDEIhS GNJIfrqo0WlriGMw6Psqrqm2yKZa/jdqJjerPLDB2D4MtwpyuSP2l67eF1jMJo8GInaK h3XPKWJ5VYz+PvWQ2yXOeQR3P5gsDppW2z7Lifg3MLHlWqZJO7zuTKlMCgGyG44lop37 b8GCNecFwraUuEIKOknJJlFr63ModdpBTn8T616aYxph2IubqP/4cq9C9x+ZXutgAawV 8ZmQ== X-Gm-Message-State: APf1xPBLNxP9DsmhtjfGwc74nVro1OlcuEI0HQQm8PZNy47G8W7tUqDV mMFWiHR+s0uqFqF1o5pcWiufqx+a X-Google-Smtp-Source: AH8x225kAnC83F3mYtVNGfPznuMzrq11Eo3I8WoxEF73RdYVjq1d/U5u8YXHl1QIVsrSHIuzD70iFw== X-Received: by 10.28.103.9 with SMTP id b9mr4141780wmc.32.1519290323103; Thu, 22 Feb 2018 01:05:23 -0800 (PST) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id p5sm13736771wmd.9.2018.02.22.01.05.22 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 22 Feb 2018 01:05:22 -0800 (PST) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Thu, 22 Feb 2018 09:05:14 +0000 Message-Id: <20180222090514.9713-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180222080907.14716-1-tvrtko.ursulin@linux.intel.com> References: <20180222080907.14716-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [RFC v2] drm/i915: Eliminate devid sprinkle X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jani Nikula MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Introduce subplatform mask to eliminate throughout the code devid checking sprinkle, mostly courtesy of IS_*_UL[TX] macros. Subplatform mask initialization is moved either to static tables (Ironlake M) or runtime device info init (Pineview, Haswell, Broadwell, Skylake, Kabylake, Coffeelake and Cannonlake). text data bss dec hex filename 1673630 59691 5064 1738385 1a8691 i915.ko.0 1673536 59691 5064 1738291 1a8633 i915.ko.1 v2: Fixed IS_SUBPLATFORM. Updated commit msg. Signed-off-by: Tvrtko Ursulin Suggested-by: Chris Wilson Cc: Chris Wilson Cc: Jani Nikula --- drivers/gpu/drm/i915/i915_drv.c | 3 +- drivers/gpu/drm/i915/i915_drv.h | 58 ++++++++++++------------------ drivers/gpu/drm/i915/i915_pci.c | 3 ++ drivers/gpu/drm/i915/intel_device_info.c | 61 +++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/intel_device_info.h | 23 +++++++++++- 5 files changed, 110 insertions(+), 38 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index aaa861b51024..ca624285c96e 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -905,7 +905,8 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv, device_info->device_id = dev_priv->drm.pdev->device; BUILD_BUG_ON(INTEL_MAX_PLATFORMS > - sizeof(device_info->platform_mask) * BITS_PER_BYTE); + sizeof(device_info->platform_subplatform_mask) * + BITS_PER_BYTE - INTEL_SUBPLATFORM_BITS); BUG_ON(device_info->gen > sizeof(device_info->gen_mask) * BITS_PER_BYTE); spin_lock_init(&dev_priv->irq_lock); spin_lock_init(&dev_priv->gpu_error.lock); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 82a106b1bdbc..808d957ce9ba 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2587,7 +2587,11 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_REVID(p, since, until) \ (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until)) -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p)) +#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_subplatform_mask & BIT(p)) +#define IS_SUBPLATFORM(dev_priv, p, s) \ + (IS_PLATFORM(dev_priv, p) && \ + ((dev_priv)->info.platform_subplatform_mask & \ + BIT(32 - INTEL_SUBPLATFORM_BITS + INTEL_SUBPLATFORM_##s))) #define IS_I830(dev_priv) IS_PLATFORM(dev_priv, INTEL_I830) #define IS_I845G(dev_priv) IS_PLATFORM(dev_priv, INTEL_I845G) @@ -2602,11 +2606,15 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_G45(dev_priv) IS_PLATFORM(dev_priv, INTEL_G45) #define IS_GM45(dev_priv) IS_PLATFORM(dev_priv, INTEL_GM45) #define IS_G4X(dev_priv) (IS_G45(dev_priv) || IS_GM45(dev_priv)) -#define IS_PINEVIEW_G(dev_priv) (INTEL_DEVID(dev_priv) == 0xa001) -#define IS_PINEVIEW_M(dev_priv) (INTEL_DEVID(dev_priv) == 0xa011) +#define IS_PINEVIEW_G(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_PINEVIEW, PINEVIEW_G) +#define IS_PINEVIEW_M(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_PINEVIEW, PINEVIEW_M) #define IS_PINEVIEW(dev_priv) IS_PLATFORM(dev_priv, INTEL_PINEVIEW) #define IS_G33(dev_priv) IS_PLATFORM(dev_priv, INTEL_G33) -#define IS_IRONLAKE_M(dev_priv) (INTEL_DEVID(dev_priv) == 0x0046) +#define IS_IRONLAKE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IRONLAKE) +#define IS_IRONLAKE_M(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_IRONLAKE, IRONLAKE_M) #define IS_IVYBRIDGE(dev_priv) IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE) #define IS_IVB_GT1(dev_priv) (IS_IVYBRIDGE(dev_priv) && \ (dev_priv)->info.gt == 1) @@ -2624,38 +2632,19 @@ intel_info(const struct drm_i915_private *dev_priv) #define IS_MOBILE(dev_priv) ((dev_priv)->info.is_mobile) #define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \ (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00) -#define IS_BDW_ULT(dev_priv) (IS_BROADWELL(dev_priv) && \ - ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 || \ - (INTEL_DEVID(dev_priv) & 0xf) == 0xb || \ - (INTEL_DEVID(dev_priv) & 0xf) == 0xe)) -/* ULX machines are also considered ULT. */ -#define IS_BDW_ULX(dev_priv) (IS_BROADWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0xf) == 0xe) +#define IS_BDW_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, ULT) +#define IS_BDW_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_BROADWELL, ULX) #define IS_BDW_GT3(dev_priv) (IS_BROADWELL(dev_priv) && \ (dev_priv)->info.gt == 3) -#define IS_HSW_ULT(dev_priv) (IS_HASWELL(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00) +#define IS_HSW_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, ULT) #define IS_HSW_GT3(dev_priv) (IS_HASWELL(dev_priv) && \ (dev_priv)->info.gt == 3) /* ULX machines are also considered ULT. */ -#define IS_HSW_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x0A0E || \ - INTEL_DEVID(dev_priv) == 0x0A1E) -#define IS_SKL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x1906 || \ - INTEL_DEVID(dev_priv) == 0x1913 || \ - INTEL_DEVID(dev_priv) == 0x1916 || \ - INTEL_DEVID(dev_priv) == 0x1921 || \ - INTEL_DEVID(dev_priv) == 0x1926) -#define IS_SKL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x190E || \ - INTEL_DEVID(dev_priv) == 0x1915 || \ - INTEL_DEVID(dev_priv) == 0x191E) -#define IS_KBL_ULT(dev_priv) (INTEL_DEVID(dev_priv) == 0x5906 || \ - INTEL_DEVID(dev_priv) == 0x5913 || \ - INTEL_DEVID(dev_priv) == 0x5916 || \ - INTEL_DEVID(dev_priv) == 0x5921 || \ - INTEL_DEVID(dev_priv) == 0x5926) -#define IS_KBL_ULX(dev_priv) (INTEL_DEVID(dev_priv) == 0x590E || \ - INTEL_DEVID(dev_priv) == 0x5915 || \ - INTEL_DEVID(dev_priv) == 0x591E) +#define IS_HSW_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_HASWELL, ULX) +#define IS_SKL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, ULT) +#define IS_SKL_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_SKYLAKE, ULX) +#define IS_KBL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, ULT) +#define IS_KBL_ULX(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_KABYLAKE, ULX) #define IS_SKL_GT2(dev_priv) (IS_SKYLAKE(dev_priv) && \ (dev_priv)->info.gt == 2) #define IS_SKL_GT3(dev_priv) (IS_SKYLAKE(dev_priv) && \ @@ -2666,14 +2655,13 @@ intel_info(const struct drm_i915_private *dev_priv) (dev_priv)->info.gt == 2) #define IS_KBL_GT3(dev_priv) (IS_KABYLAKE(dev_priv) && \ (dev_priv)->info.gt == 3) -#define IS_CFL_ULT(dev_priv) (IS_COFFEELAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0) +#define IS_CFL_ULT(dev_priv) IS_SUBPLATFORM(dev_priv, INTEL_COFFEELAKE, ULT) #define IS_CFL_GT2(dev_priv) (IS_COFFEELAKE(dev_priv) && \ (dev_priv)->info.gt == 2) #define IS_CFL_GT3(dev_priv) (IS_COFFEELAKE(dev_priv) && \ (dev_priv)->info.gt == 3) -#define IS_CNL_WITH_PORT_F(dev_priv) (IS_CANNONLAKE(dev_priv) && \ - (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004) +#define IS_CNL_WITH_PORT_F(dev_priv) \ + IS_SUBPLATFORM(dev_priv, INTEL_CANNONLAKE, PORTF) #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 1eaabf28d7b7..9e2967f7c583 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -30,6 +30,7 @@ #include "i915_selftest.h" #define PLATFORM(x) .platform = (x), .platform_mask = BIT(x) +#define SUBPLATFORM(x) .subplatform_mask = BIT(INTEL_SUBPLATFORM_##x) #define GEN(x) .gen = (x), .gen_mask = BIT((x) - 1) #define GEN_DEFAULT_PIPEOFFSETS \ @@ -234,6 +235,7 @@ static const struct intel_device_info intel_ironlake_d_info = { static const struct intel_device_info intel_ironlake_m_info = { GEN5_FEATURES, PLATFORM(INTEL_IRONLAKE), + SUBPLATFORM(IRONLAKE_M), .is_mobile = 1, .has_fbc = 1, }; @@ -605,6 +607,7 @@ static const struct intel_device_info intel_icelake_11_info = { #undef GEN #undef PLATFORM +#undef SUBPLATFORM /* * Make sure any device matches here are from most specific to most diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c index 298f8996cc54..5beb2cbde3b5 100644 --- a/drivers/gpu/drm/i915/intel_device_info.c +++ b/drivers/gpu/drm/i915/intel_device_info.c @@ -111,10 +111,11 @@ void intel_device_info_dump(const struct intel_device_info *info, struct drm_i915_private *dev_priv = container_of(info, struct drm_i915_private, info); - drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s gen=%i\n", + drm_printf(p, "pciid=0x%04x rev=0x%02x platform=%s (subplatform=%x) gen=%i\n", INTEL_DEVID(dev_priv), INTEL_REVID(dev_priv), intel_platform_name(info->platform), + info->subplatform_mask, info->gen); intel_device_info_dump_flags(info, p); @@ -458,6 +459,62 @@ static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv) return 0; } +static void intel_device_info_subplatform_init(struct intel_device_info *info) +{ + struct drm_i915_private *i915 = + container_of(info, struct drm_i915_private, info); + u16 devid = INTEL_DEVID(i915); + + if (IS_PINEVIEW(i915)) { + if (devid == 0xa001) + info->subplatform_mask = INTEL_SUBPLATFORM_PINEVIEW_G; + else if (devid == 0xa011) + info->subplatform_mask = INTEL_SUBPLATFORM_PINEVIEW_M; + } else if (IS_HASWELL(i915)) { + if ((devid & 0xFF00) == 0x0A00) + info->subplatform_mask = INTEL_SUBPLATFORM_ULT; + /* ULX machines are also considered ULT. */ + if (devid == 0x0A0E || devid == 0x0A1E) + info->subplatform_mask |= INTEL_SUBPLATFORM_ULX; + } else if (IS_BROADWELL(i915)) { + if ((devid & 0xf) == 0x6 || + (devid & 0xf) == 0xb || + (devid & 0xf) == 0xe) + info->subplatform_mask = INTEL_SUBPLATFORM_ULT; + /* ULX machines are also considered ULT. */ + if ((devid & 0xf) == 0xe) + info->subplatform_mask |= INTEL_SUBPLATFORM_ULX; + } else if (IS_SKYLAKE(i915)) { + if (devid == 0x1906 || + devid == 0x1913 || + devid == 0x1916 || + devid == 0x1921 || + devid == 0x1926) + info->subplatform_mask = INTEL_SUBPLATFORM_ULT; + else if (devid == 0x190E || + devid == 0x1915 || + devid == 0x191E) + info->subplatform_mask = INTEL_SUBPLATFORM_ULX; + } else if (IS_KABYLAKE(i915)) { + if (devid == 0x5906 || + devid == 0x5913 || + devid == 0x5916 || + devid == 0x5921 || + devid == 0x5926) + info->subplatform_mask = INTEL_SUBPLATFORM_ULT; + else if (devid == 0x590E || + devid == 0x5915 || + devid == 0x591E) + info->subplatform_mask = INTEL_SUBPLATFORM_ULX; + } else if (IS_COFFEELAKE(i915)) { + if ((devid & 0x00F0) == 0x00A0) + info->subplatform_mask = INTEL_SUBPLATFORM_ULT; + } else if (IS_CANNONLAKE(i915)) { + if ((devid & 0x0004) == 0x0004) + info->subplatform_mask = INTEL_SUBPLATFORM_PORTF; + } +} + /** * intel_device_info_runtime_init - initialize runtime info * @info: intel device info struct @@ -480,6 +537,8 @@ void intel_device_info_runtime_init(struct intel_device_info *info) container_of(info, struct drm_i915_private, info); enum pipe pipe; + intel_device_info_subplatform_init(info); + if (INTEL_GEN(dev_priv) >= 10) { for_each_pipe(dev_priv, pipe) info->num_scalers[pipe] = 2; diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 71fdfb0451ef..7b6211061fba 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -74,6 +74,20 @@ enum intel_platform { INTEL_MAX_PLATFORMS }; +/* Subplatform flags share the same namespace per parent platform. */ + +#define INTEL_SUBPLATFORM_BITS (2) + +#define INTEL_SUBPLATFORM_IRONLAKE_M (0) + +#define INTEL_SUBPLATFORM_PINEVIEW_G (0) +#define INTEL_SUBPLATFORM_PINEVIEW_M (1) + +#define INTEL_SUBPLATFORM_ULT (0) +#define INTEL_SUBPLATFORM_ULX (1) + +#define INTEL_SUBPLATFORM_PORTF (0) + #define DEV_INFO_FOR_EACH_FLAG(func) \ func(is_mobile); \ func(is_lp); \ @@ -135,7 +149,14 @@ struct intel_device_info { u8 ring_mask; /* Rings supported by the HW */ enum intel_platform platform; - u32 platform_mask; + + union { + u32 platform_subplatform_mask; + struct { + u32 platform_mask : (32 - INTEL_SUBPLATFORM_BITS); + u32 subplatform_mask : INTEL_SUBPLATFORM_BITS; + }; + }; u32 display_mmio_offset;