| Message ID | 20180224020311.14813-3-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Fri, 2018-02-23 at 18:03 -0800, José Roberto de Souza wrote: > As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR > and wait until it is back to inactive state before do any aux ch > transaction. > I wonder if we need this for CHV/VLV since the HW does not send PSR aux transactions on it's own. > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > --- > drivers/gpu/drm/i915/intel_dp.c | 8 +++++++- > drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ > drivers/gpu/drm/i915/intel_psr.c | 42 ++++++++++++++++++++++++++++++++++------ > 3 files changed, 52 insertions(+), 7 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c > index 7be2fec51651..dacdd98bbb2e 100644 > --- a/drivers/gpu/drm/i915/intel_dp.c > +++ b/drivers/gpu/drm/i915/intel_dp.c > @@ -1088,8 +1088,14 @@ static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp) > to_i915(intel_dig_port->base.base.dev); > i915_reg_t ch_mutex; > > - if (!intel_dp->aux_ch_mutex_reg) > + if (!intel_dp->aux_ch_mutex_reg) { > + /* As gen < 9 hardware don't have the aux ch mutex, we need to > + * exit PSR and wait until it is back to inactive state before > + * do any aux ch transaction > + */ > + intel_psr_exit(intel_dp, true); > return true; > + } > > ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp); > I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE); > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h > index 267cc6c5a89f..7adcd5955d1b 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -1881,6 +1881,15 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, > unsigned frontbuffer_bits); > void intel_psr_compute_config(struct intel_dp *intel_dp, > struct intel_crtc_state *crtc_state); > +/** > + * Exit PSR in the given DisplayPort. > + * @intel_dp: DisplayPort which PSR should be exit if running > + * @wait_exit: if true it will wait until PSR have changed to inactive state, > + * otherwise there is not wait. > + * > + * It will also schedule a work to try to active PSR again. > + */ > +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit); > > /* intel_runtime_pm.c */ > int intel_power_domains_init(struct drm_i915_private *); > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index e8c32c3afb0e..0b889c85e8da 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -56,6 +56,8 @@ > #include "intel_drv.h" > #include "i915_drv.h" > > +#define PSR_ACTIVE_DELAY_MSEC 100 > + > static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) > { > struct drm_i915_private *dev_priv = to_i915(dev); > @@ -486,6 +488,16 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, > } > } > > +static void intel_psr_active_schedule(struct i915_psr *psr, > + unsigned int msec_delay) > +{ > + if (psr->active || psr->busy_frontbuffer_bits) > + return; > + > + if (!work_busy(&psr->work.work)) > + schedule_delayed_work(&psr->work, msecs_to_jiffies(msec_delay)); This change will conflict with https://patchwork.freedesktop.org/series/38199/ > +} > + > /** > * intel_psr_enable - Enable PSR > * @intel_dp: Intel DP > @@ -534,8 +546,9 @@ void intel_psr_enable(struct intel_dp *intel_dp, > * - On HSW/BDW we get a recoverable frozen screen until > * next exit-activate sequence. > */ > - schedule_delayed_work(&dev_priv->psr.work, > - msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); > + intel_psr_active_schedule(&dev_priv->psr, > + intel_dp->panel_power_cycle_delay > + * 5); > } > > unlock: > @@ -886,10 +899,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, > if (frontbuffer_bits) > dev_priv->psr.exit(dev_priv->psr.enabled, false); > > - if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) > - if (!work_busy(&dev_priv->psr.work.work)) > - schedule_delayed_work(&dev_priv->psr.work, > - msecs_to_jiffies(100)); > + intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC); > mutex_unlock(&dev_priv->psr.lock); > } > > @@ -955,3 +965,23 @@ void intel_psr_init(struct drm_i915_private *dev_priv) > dev_priv->psr.exit = hsw_psr_exit; > } > } > + > +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit) > +{ > + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); > + struct drm_device *dev = intel_dig_port->base.base.dev; > + struct drm_i915_private *dev_priv = to_i915(dev); > + > + if (!HAS_PSR(dev_priv)) > + return; > + > + mutex_lock(&dev_priv->psr.lock); > + > + if (dev_priv->psr.enabled != intel_dp) > + goto out; > + > + dev_priv->psr.exit(intel_dp, wait_exit); > + intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC); psr_exit scheduling an activate looks wrong and it is also exactly what psr_flush does. I suppose we could call psr_invalidate at the beginning of the aux transaction and psr_flush at the end. But the question is what arguments do we pass to those functions. Or we could just call psr_exit at the start (without scheduling activate) and psr_activate at the end. > +out: > + mutex_unlock(&dev_priv->psr.lock); > +}
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 7be2fec51651..dacdd98bbb2e 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1088,8 +1088,14 @@ static bool intel_dp_aux_ch_trylock(struct intel_dp *intel_dp) to_i915(intel_dig_port->base.base.dev); i915_reg_t ch_mutex; - if (!intel_dp->aux_ch_mutex_reg) + if (!intel_dp->aux_ch_mutex_reg) { + /* As gen < 9 hardware don't have the aux ch mutex, we need to + * exit PSR and wait until it is back to inactive state before + * do any aux ch transaction + */ + intel_psr_exit(intel_dp, true); return true; + } ch_mutex = intel_dp->aux_ch_mutex_reg(intel_dp); I915_WRITE(ch_mutex, DP_AUX_CH_MUTEX_ENABLE); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 267cc6c5a89f..7adcd5955d1b 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1881,6 +1881,15 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); +/** + * Exit PSR in the given DisplayPort. + * @intel_dp: DisplayPort which PSR should be exit if running + * @wait_exit: if true it will wait until PSR have changed to inactive state, + * otherwise there is not wait. + * + * It will also schedule a work to try to active PSR again. + */ +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit); /* intel_runtime_pm.c */ int intel_power_domains_init(struct drm_i915_private *); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index e8c32c3afb0e..0b889c85e8da 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -56,6 +56,8 @@ #include "intel_drv.h" #include "i915_drv.h" +#define PSR_ACTIVE_DELAY_MSEC 100 + static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -486,6 +488,16 @@ static void hsw_psr_enable_source(struct intel_dp *intel_dp, } } +static void intel_psr_active_schedule(struct i915_psr *psr, + unsigned int msec_delay) +{ + if (psr->active || psr->busy_frontbuffer_bits) + return; + + if (!work_busy(&psr->work.work)) + schedule_delayed_work(&psr->work, msecs_to_jiffies(msec_delay)); +} + /** * intel_psr_enable - Enable PSR * @intel_dp: Intel DP @@ -534,8 +546,9 @@ void intel_psr_enable(struct intel_dp *intel_dp, * - On HSW/BDW we get a recoverable frozen screen until * next exit-activate sequence. */ - schedule_delayed_work(&dev_priv->psr.work, - msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); + intel_psr_active_schedule(&dev_priv->psr, + intel_dp->panel_power_cycle_delay + * 5); } unlock: @@ -886,10 +899,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, if (frontbuffer_bits) dev_priv->psr.exit(dev_priv->psr.enabled, false); - if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) - if (!work_busy(&dev_priv->psr.work.work)) - schedule_delayed_work(&dev_priv->psr.work, - msecs_to_jiffies(100)); + intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC); mutex_unlock(&dev_priv->psr.lock); } @@ -955,3 +965,23 @@ void intel_psr_init(struct drm_i915_private *dev_priv) dev_priv->psr.exit = hsw_psr_exit; } } + +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_exit) +{ + struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = intel_dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + if (!HAS_PSR(dev_priv)) + return; + + mutex_lock(&dev_priv->psr.lock); + + if (dev_priv->psr.enabled != intel_dp) + goto out; + + dev_priv->psr.exit(intel_dp, wait_exit); + intel_psr_active_schedule(&dev_priv->psr, PSR_ACTIVE_DELAY_MSEC); +out: + mutex_unlock(&dev_priv->psr.lock); +}
As gen < 9 hardware don't have the aux ch mutex, we need to exit PSR and wait until it is back to inactive state before do any aux ch transaction. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> --- drivers/gpu/drm/i915/intel_dp.c | 8 +++++++- drivers/gpu/drm/i915/intel_drv.h | 9 +++++++++ drivers/gpu/drm/i915/intel_psr.c | 42 ++++++++++++++++++++++++++++++++++------ 3 files changed, 52 insertions(+), 7 deletions(-)