From patchwork Thu Mar 8 17:13:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10268517 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 47F9F6037E for ; Thu, 8 Mar 2018 17:13:59 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 37457297A4 for ; Thu, 8 Mar 2018 17:13:59 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2BE8F297C7; Thu, 8 Mar 2018 17:13:59 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 1E517297A4 for ; Thu, 8 Mar 2018 17:13:58 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 5661F6EAB9; Thu, 8 Mar 2018 17:13:57 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5DA756EAB3; Thu, 8 Mar 2018 17:13:55 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 10952475-1500050 for multiple; Thu, 08 Mar 2018 17:13:42 +0000 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Thu, 08 Mar 2018 17:13:36 +0000 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 8 Mar 2018 17:13:35 +0000 Message-Id: <20180308171335.31595-1-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.16.2 MIME-Version: 1.0 X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH igt] igt: Add gem_ctx_freq to exercise requesting freq on a ctx X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paneri@freedesktop.org, Kamble@freedesktop.org, igt-dev@lists.freedesktop.org, Praveen Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Exercise some new API that allows applications to request that individual contexts are executed within a desired frequency range. v2: Split single/continuous set_freq subtests Signed-off-by: Chris Wilson Cc: Paneri, Praveen Cc: Kamble, Sagar A Cc: Antonio Argenziano --- tests/Makefile.am | 1 + tests/Makefile.sources | 1 + tests/gem_ctx_freq.c | 604 +++++++++++++++++++++++++++++++++++++++++++++++++ tests/meson.build | 1 + 4 files changed, 607 insertions(+) create mode 100644 tests/gem_ctx_freq.c diff --git a/tests/Makefile.am b/tests/Makefile.am index dbc7be72..389f7fc7 100644 --- a/tests/Makefile.am +++ b/tests/Makefile.am @@ -104,6 +104,7 @@ drm_import_export_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) drm_import_export_LDADD = $(LDADD) -lpthread gem_close_race_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_close_race_LDADD = $(LDADD) -lpthread +gem_ctx_freq_LDADD = $(LDADD) $(top_builddir)/lib/libigt_perf.la gem_ctx_thrash_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) gem_ctx_thrash_LDADD = $(LDADD) -lpthread gem_exec_parallel_CFLAGS = $(AM_CFLAGS) $(THREAD_CFLAGS) diff --git a/tests/Makefile.sources b/tests/Makefile.sources index 4a81ac4a..3d079c42 100644 --- a/tests/Makefile.sources +++ b/tests/Makefile.sources @@ -58,6 +58,7 @@ TESTS_progs = \ gem_ctx_bad_exec \ gem_ctx_create \ gem_ctx_exec \ + gem_ctx_freq \ gem_ctx_isolation \ gem_ctx_param \ gem_ctx_switch \ diff --git a/tests/gem_ctx_freq.c b/tests/gem_ctx_freq.c new file mode 100644 index 00000000..f7e79ac3 --- /dev/null +++ b/tests/gem_ctx_freq.c @@ -0,0 +1,604 @@ +/* + * Copyright © 2018 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "igt.h" +#include "igt_perf.h" + +#define LOCAL_CONTEXT_PARAM_FREQUENCY 8 + +#define SAMPLE_PERIOD (USEC_PER_SEC / 10) + +static int __set_freq(int fd, uint32_t ctx, uint32_t min, uint32_t max) +{ + struct drm_i915_gem_context_param param = { + .ctx_id = ctx, + .param = LOCAL_CONTEXT_PARAM_FREQUENCY, + .value = (uint64_t)max << 32 | min, + }; + + return __gem_context_set_param(fd, ¶m); +} + +static void set_freq(int fd, uint32_t ctx, uint32_t min, uint32_t max) +{ + igt_assert_eq(__set_freq(fd, ctx, min, max), 0); +} + +static void get_freq(int fd, uint32_t ctx, uint32_t *min, uint32_t *max) +{ + struct drm_i915_gem_context_param param = { + .ctx_id = ctx, + .param = LOCAL_CONTEXT_PARAM_FREQUENCY, + }; + + gem_context_get_param(fd, ¶m); + + *min = param.value & 0xffffffff; + *max = param.value >> 32; +} + +static double measure_frequency(int pmu, int period_us) +{ + uint64_t data[2]; + uint64_t d_t, d_v; + + igt_assert_eq(read(pmu, data, sizeof(data)), sizeof(data)); + d_v = -data[0]; + d_t = -data[1]; + + usleep(period_us); + + igt_assert_eq(read(pmu, data, sizeof(data)), sizeof(data)); + d_v += data[0]; + d_t += data[1]; + + return d_v * 1e9 / d_t; +} + +static void single(int fd, const struct intel_execution_engine *e) +{ + const unsigned int engine = e->exec_id | e->flags; + uint32_t ctx = gem_context_create(fd); + uint32_t min, max; + double measured; + igt_spin_t *spin; + int pmu; + + get_freq(fd, ctx, &min, &max); + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + for (uint32_t freq = min + 50; freq <= max; freq += 100) { + uint32_t cur, discard; + + set_freq(fd, ctx, freq, freq); + get_freq(fd, ctx, &cur, &discard); + + gem_quiescent_gpu(fd); + spin = __igt_spin_batch_new(fd, ctx, engine, 0); + usleep(10000); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + + igt_spin_batch_free(fd, spin); + igt_info("%s(single): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, cur); + igt_assert(measured > cur - 100 && measured < cur + 100); + } + gem_quiescent_gpu(fd); + + close(pmu); + gem_context_destroy(fd, ctx); +} + +static void continuous(int fd, const struct intel_execution_engine *e) +{ + const unsigned int engine = e->exec_id | e->flags; + uint32_t ctx = gem_context_create(fd); + uint32_t min, max; + double measured; + igt_spin_t *spin; + int pmu; + + get_freq(fd, ctx, &min, &max); + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + gem_quiescent_gpu(fd); + spin = __igt_spin_batch_new(fd, ctx, engine, 0); + for (uint32_t freq = min + 50; freq <= max; freq += 100) { + uint32_t cur, discard; + igt_spin_t *kick; + + set_freq(fd, ctx, freq, freq); + get_freq(fd, ctx, &cur, &discard); + + /* + * When requesting a new frequency on the currently + * executing context, it does not take effect until the + * next context switch. In this case, we trigger a lite + * restore. + */ + kick = __igt_spin_batch_new(fd, ctx, engine, 0); + igt_spin_batch_free(fd, spin); + spin = kick; + + usleep(10000); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + + igt_info("%s(continuous): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, cur); + igt_assert(measured > cur - 100 && measured < cur + 100); + } + igt_spin_batch_free(fd, spin); + gem_quiescent_gpu(fd); + + close(pmu); + gem_context_destroy(fd, ctx); +} + +static void inflight(int fd, const struct intel_execution_engine *e) +{ + const unsigned int engine = e->exec_id | e->flags; + uint32_t ctx, min, max, freq, discard; + double measured; + igt_spin_t *plug, *work[2]; + int pmu; + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + ctx = gem_context_create(fd); + get_freq(fd, ctx, &min, &max); + set_freq(fd, ctx, min, min); + + igt_info("Min freq: %dMHz; Max freq: %dMHz\n", min, max); + + gem_quiescent_gpu(fd); + plug = igt_spin_batch_new(fd, ctx, engine, 0); + gem_context_destroy(fd, ctx); + for (int n = 0; n < 16; n++) { + struct drm_i915_gem_exec_object2 obj = { + .handle = plug->handle, + }; + struct drm_i915_gem_execbuffer2 eb = { + .buffer_count = 1, + .buffers_ptr = to_user_pointer(&obj), + .flags = engine, + .rsvd1 = gem_context_create(fd), + }; + set_freq(fd, eb.rsvd1, min, min); + gem_execbuf(fd, &eb); + gem_context_destroy(fd, eb.rsvd1); + } + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("%s(plug): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, min); + igt_assert(measured > min - 100 && measured < min + 100); + + ctx = gem_context_create(fd); + set_freq(fd, ctx, max, max); + work[0] = __igt_spin_batch_new(fd, ctx, engine, 0); + + /* work is now queued but not executing */ + freq = (max + min) / 2; + set_freq(fd, ctx, freq, freq); + get_freq(fd, ctx, &freq, &discard); + gem_context_destroy(fd, ctx); + + ctx = gem_context_create(fd); + set_freq(fd, ctx, max, max); + work[1] = __igt_spin_batch_new(fd, ctx, engine, 0); + gem_context_destroy(fd, ctx); + + igt_spin_batch_end(plug); + do + usleep(10000); + while (gem_bo_busy(fd, plug->handle)); + igt_spin_batch_free(fd, plug); + + /* Now work will execute */ + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_engine_info"); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("%s(work0): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, freq); + igt_assert(measured > freq - 100 && measured < freq + 100); + + igt_spin_batch_end(work[0]); + do + usleep(10000); + while (gem_bo_busy(fd, work[0]->handle)); + igt_spin_batch_free(fd, work[0]); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_engine_info"); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("%s(work1): Measured %.1fMHz, expected %dMhz\n", + e->name, measured, max); + igt_assert(measured > max - 100 && measured < max + 100); + + igt_spin_batch_free(fd, work[1]); + close(pmu); + gem_quiescent_gpu(fd); +} + +static void sandwich(int fd) +{ + uint32_t ctx = gem_context_create(fd); + unsigned int engine; + uint32_t min, max; + igt_spin_t *spin; + int pmu; + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + spin = igt_spin_batch_new(fd, ctx, 0, 0); + get_freq(fd, ctx, &min, &max); + set_freq(fd, ctx, min, min); + for_each_physical_engine(fd, engine) { + struct drm_i915_gem_exec_object2 obj = { + .handle = spin->handle, + }; + struct drm_i915_gem_execbuffer2 eb = { + .buffer_count = 1, + .buffers_ptr = to_user_pointer(&obj), + .flags = engine, + .rsvd1 = ctx, + }; + uint32_t cur, discard; + double measured; + + min += 50; + if (min > max) + break; + + set_freq(fd, ctx, min, min); + get_freq(fd, ctx, &cur, &discard); + + gem_execbuf(fd, &eb); + usleep(10000); + + measured = measure_frequency(pmu, SAMPLE_PERIOD); + igt_debugfs_dump(fd, "i915_rps_boost_info"); + + igt_info("Measured %.1fMHz, expected %dMhz\n", measured, cur); + igt_assert(measured > cur - 100 && measured < cur + 100); + } + igt_spin_batch_free(fd, spin); + gem_quiescent_gpu(fd); + + gem_context_destroy(fd, ctx); + close(pmu); +} + +static void pwm(int fd, unsigned int *engines, unsigned int nengine, int link) +{ + uint32_t ctx[nengine]; + + fcntl(link, F_SETFL, fcntl(fd, F_GETFL) | O_NONBLOCK); + + for (unsigned int n = 0; n < nengine; n++) + ctx[n] = gem_context_create(fd); + + do { + igt_spin_t *spin; + struct { + uint32_t engine; + uint32_t min; + uint32_t max; + } req; + + while (read(link, &req, sizeof(req)) > 0) { + if ((req.engine | req.min | req.max) == 0) + goto out; + + igt_assert(req.engine < nengine); + set_freq(fd, ctx[req.engine], req.min, req.max); + } + + /* Create a 20% load using busy spinners */ + spin = __igt_spin_batch_new(fd, ctx[0], engines[0], 0); + for (unsigned int n = 1; n < nengine; n++) { + struct drm_i915_gem_exec_object2 obj = { + .handle = spin->handle, + }; + struct drm_i915_gem_execbuffer2 eb = { + .buffer_count = 1, + .buffers_ptr = to_user_pointer(&obj), + .flags = engines[n], + .rsvd1 = ctx[n], + }; + gem_execbuf(fd, &eb); + } + usleep(100); + igt_spin_batch_end(spin); + + do + usleep(10); + while (gem_bo_busy(fd, spin->handle)); + igt_spin_batch_free(fd, spin); + usleep(400); + } while (1); + +out: + for (unsigned int n = 0; n < nengine; n++) + gem_context_destroy(fd, ctx[n]); +} + +static void smoketest(int fd, int timeout) +{ + unsigned int engines[16]; + unsigned int nengine; + unsigned int engine; + uint32_t min[16], max[16]; + int pmu, link[2]; + + get_freq(fd, 0, &min[0], &max[0]); + + nengine = 0; + for_each_physical_engine(fd, engine) { + if (nengine == ARRAY_SIZE(engines) - 1) + break; + + min[nengine] = min[0]; + max[nengine] = max[0]; + engines[nengine] = engine; + nengine++; + } + igt_require(nengine); + + igt_assert(pipe(link) == 0); + igt_fork(child, 1) + pwm(fd, engines, nengine, link[0]); + close(link[0]); + + pmu = perf_i915_open(I915_PMU_REQUESTED_FREQUENCY); + igt_require(pmu >= 0); + + igt_until_timeout(timeout) { + struct { + uint32_t engine; + uint32_t min; + uint32_t max; + } req; + double measured; + uint32_t ctx; + + req.engine = rand() % nengine; + + ctx = gem_context_create(fd); + get_freq(fd, ctx, &req.min, &req.max); + req.min = rand() % (req.max - req.min) + req.min; + req.max = rand() % (req.max - req.min) + req.min; + set_freq(fd, ctx, req.min, req.max); + get_freq(fd, ctx, &req.min, &req.max); + + igt_debug("Replacing (%d, %d) on engine %x with (%d, %d)\n", + min[req.engine], max[req.engine], req.engine, + req.min, req.max); + igt_assert(write(link[1], &req, sizeof(req)) == sizeof(req)); + gem_context_destroy(fd, ctx); + + min[req.engine] = req.min; + max[req.engine] = req.max; + + for (unsigned int n = 0; n < nengine; n++) { + igt_debug("[%d]: [%d, %d]\n", n, min[n], max[n]); + if (min[n] < req.min) + req.min = min[n]; + if (max[n] > req.max) + req.max = max[n]; + } + igt_assert(req.max >= req.min); + + usleep(50000); + measured = measure_frequency(pmu, SAMPLE_PERIOD); + + if (measured <= req.min - 100 || measured >= req.max + 100) + igt_debugfs_dump(fd, "i915_rps_boost_info"); + igt_info("Measured %.1fMHz, expected [%d, %d]Mhz\n", + measured, req.min, req.max); + igt_assert(measured > req.min - 100 && + measured < req.max + 100); + } + + do { + struct { + uint32_t engine; + uint32_t min; + uint32_t max; + } req = {}; + + write(link[1], &req, sizeof(req)); + close(link[1]); + } while (0); + igt_waitchildren(); + gem_quiescent_gpu(fd); + + close(pmu); +} + +static void invalid_param(int fd) +{ + uint32_t min, max; + uint32_t cur_min, cur_max; + + get_freq(fd, 0, &min, &max); + + igt_assert_eq(__set_freq(fd, 0, min - 50, max), -EINVAL); + igt_assert_eq(__set_freq(fd, 0, min, max + 50), -EINVAL); + igt_assert_eq(__set_freq(fd, 0, min + 50, min), -EINVAL); + igt_assert_eq(__set_freq(fd, 0, max, max - 50), -EINVAL); + + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); +} + +static void idempotent(int fd) +{ + uint32_t min, max; + uint32_t cur_min, cur_max; + + get_freq(fd, 0, &min, &max); + + set_freq(fd, 0, max, max); + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, max); + igt_assert_eq(cur_max, max); + + set_freq(fd, 0, min, min); + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, min); + + set_freq(fd, 0, min, max); + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); +} + +static void independent(int fd) +{ + uint32_t min, max; + uint32_t cur_min, cur_max; + uint32_t ctx[2]; + + get_freq(fd, 0, &min, &max); + + set_freq(fd, 0, max, max); + ctx[0] = gem_context_create(fd); + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + set_freq(fd, 0, min, min); + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + ctx[1] = gem_context_create(fd); + get_freq(fd, ctx[1], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + set_freq(fd, ctx[1], max, max); + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + + get_freq(fd, 0, &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, min); + + get_freq(fd, ctx[1], &cur_min, &cur_max); + igt_assert_eq(cur_min, max); + igt_assert_eq(cur_max, max); + gem_context_destroy(fd, ctx[1]); + + get_freq(fd, ctx[0], &cur_min, &cur_max); + igt_assert_eq(cur_min, min); + igt_assert_eq(cur_max, max); + gem_context_destroy(fd, ctx[0]); +} + +static bool has_ctx_freq(int fd) +{ + struct drm_i915_gem_context_param param = { + .param = LOCAL_CONTEXT_PARAM_FREQUENCY, + }; + + return __gem_context_get_param(fd, ¶m) == 0; +} + +igt_main +{ + const struct intel_execution_engine *e; + int fd = -1; + + igt_fixture { + fd = drm_open_driver(DRIVER_INTEL); + igt_require_gem(fd); + + igt_require(has_ctx_freq(fd)); + } + + igt_subtest("invalid") + invalid_param(fd); + + igt_subtest("idempotent") + idempotent(fd); + + igt_subtest("independent") + independent(fd); + + igt_skip_on_simulation(); + + for (e = intel_execution_engines; e->name; e++) { + if (e->exec_id == 0) + continue; + + igt_subtest_group { + igt_fixture { + igt_require(gem_ring_has_physical_engine(fd, e->exec_id | e->flags)); + } + + igt_subtest_f("%s-single", e->name) + single(fd, e); + igt_subtest_f("%s-continuous", e->name) + continuous(fd, e); + igt_subtest_f("%s-inflight", e->name) + inflight(fd, e); + } + } + + igt_subtest("sandwich") + sandwich(fd); + + igt_subtest("smoketest") + smoketest(fd, 20); +} diff --git a/tests/meson.build b/tests/meson.build index 58729231..f1271274 100644 --- a/tests/meson.build +++ b/tests/meson.build @@ -35,6 +35,7 @@ test_progs = [ 'gem_ctx_bad_exec', 'gem_ctx_create', 'gem_ctx_exec', + 'gem_ctx_freq', 'gem_ctx_param', 'gem_ctx_switch', 'gem_ctx_thrash',