From patchwork Wed Mar 14 09:37:24 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10281755 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B3309602BD for ; Wed, 14 Mar 2018 09:38:25 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A3F2E2880B for ; Wed, 14 Mar 2018 09:38:25 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 97B3428803; Wed, 14 Mar 2018 09:38:25 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2A15828803 for ; Wed, 14 Mar 2018 09:38:25 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 32BDD6E67D; Wed, 14 Mar 2018 09:38:24 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id A9B176E696 for ; Wed, 14 Mar 2018 09:38:22 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11021197-1500050 for multiple; Wed, 14 Mar 2018 09:38:20 +0000 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Wed, 14 Mar 2018 09:38:20 +0000 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Wed, 14 Mar 2018 09:37:24 +0000 Message-Id: <20180314093748.8541-12-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180314093748.8541-1-chris@chris-wilson.co.uk> References: <20180314093748.8541-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 12/36] drm/i915: Merge sbi read/write into a single accessor X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: praveen.paneri@intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Since intel_sideband_read and intel_sideband_write differ by only a couple of lines (depending on whether we feed the value in or out), merge the two into a single common accessor. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/intel_sideband.c | 93 +++++++++++++---------------------- 1 file changed, 33 insertions(+), 60 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c index 87e34787939b..e5faebb511ae 100644 --- a/drivers/gpu/drm/i915/intel_sideband.c +++ b/drivers/gpu/drm/i915/intel_sideband.c @@ -309,91 +309,64 @@ void vlv_dpio_put(struct drm_i915_private *dev_priv) } /* SBI access */ -u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, - enum intel_sbi_destination destination) +static int intel_sbi_rw(struct drm_i915_private *dev_priv, u16 reg, + enum intel_sbi_destination destination, + u32 *val, bool is_read) { - u32 value = 0; + u32 cmd; lockdep_assert_held(&dev_priv->sb_lock); - if (intel_wait_for_register(dev_priv, - SBI_CTL_STAT, SBI_BUSY, 0, - 100)) { + if (intel_wait_for_register_fw(dev_priv, + SBI_CTL_STAT, SBI_BUSY, 0, + 100)) { DRM_ERROR("timeout waiting for SBI to become ready\n"); - return 0; + return -EBUSY; } - I915_WRITE(SBI_ADDR, (reg << 16)); - I915_WRITE(SBI_DATA, 0); + I915_WRITE_FW(SBI_ADDR, (u32)reg << 16); + I915_WRITE_FW(SBI_DATA, is_read ? 0 : *val); if (destination == SBI_ICLK) - value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; + cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD; else - value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; - I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY); + cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD; + if (!is_read) + cmd |= BIT(8); + I915_WRITE_FW(SBI_CTL_STAT, cmd | SBI_BUSY); - if (intel_wait_for_register(dev_priv, - SBI_CTL_STAT, - SBI_BUSY, - 0, - 100)) { + if (__intel_wait_for_register_fw(dev_priv, + SBI_CTL_STAT, SBI_BUSY, 0, + 100, 100, &cmd)) { DRM_ERROR("timeout waiting for SBI to complete read\n"); - return 0; + return -ETIMEDOUT; } - if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) { + if (cmd & SBI_RESPONSE_FAIL) { DRM_ERROR("error during SBI read of reg %x\n", reg); - return 0; + return -ENXIO; } - return I915_READ(SBI_DATA); + if (is_read) + *val = I915_READ_FW(SBI_DATA); + + return 0; } -void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, - enum intel_sbi_destination destination) +u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg, + enum intel_sbi_destination destination) { - u32 tmp; - - lockdep_assert_held(&dev_priv->sb_lock); - - if (intel_wait_for_register(dev_priv, - SBI_CTL_STAT, SBI_BUSY, 0, - 100)) { - DRM_ERROR("timeout waiting for SBI to become ready\n"); - return; - } + u32 result = 0; - I915_WRITE(SBI_ADDR, (reg << 16)); - I915_WRITE(SBI_DATA, value); - - if (destination == SBI_ICLK) - tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR; - else - tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR; - I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp); - - if (intel_wait_for_register(dev_priv, - SBI_CTL_STAT, - SBI_BUSY, - 0, - 100)) { - DRM_ERROR("timeout waiting for SBI to complete write\n"); - return; - } + intel_sbi_rw(dev_priv, reg, destination, &result, true); - if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) { - DRM_ERROR("error during SBI write of %x to reg %x\n", - value, reg); - return; - } + return result; } -u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg) +void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value, + enum intel_sbi_destination destination) { - u32 val = 0; - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP, - reg, &val); - return val; + intel_sbi_rw(dev_priv, reg, destination, &value, false); } void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)