From patchwork Wed Mar 21 23:23:43 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Matt Roper X-Patchwork-Id: 10300687 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 135CA60349 for ; Wed, 21 Mar 2018 23:25:48 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 05734290D7 for ; Wed, 21 Mar 2018 23:25:48 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EE9862990D; Wed, 21 Mar 2018 23:25:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=unavailable version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9C412290D7 for ; Wed, 21 Mar 2018 23:25:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 86DA66EB59; Wed, 21 Mar 2018 23:25:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga05.intel.com (mga05.intel.com [192.55.52.43]) by gabe.freedesktop.org (Postfix) with ESMTPS id 377A66EB56; Wed, 21 Mar 2018 23:25:27 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga005.jf.intel.com ([10.7.209.41]) by fmsmga105.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 21 Mar 2018 16:25:26 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,341,1517904000"; d="scan'208";a="210273179" Received: from mdroper-desk.fm.intel.com ([10.1.134.220]) by orsmga005.jf.intel.com with ESMTP; 21 Mar 2018 16:25:26 -0700 From: Matt Roper To: dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, cgroups@vger.kernel.org Date: Wed, 21 Mar 2018 16:23:43 -0700 Message-Id: <20180321232344.20727-8-matthew.d.roper@intel.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180321232344.20727-1-matthew.d.roper@intel.com> References: <20180321232344.20727-1-matthew.d.roper@intel.com> Subject: [Intel-gfx] [PATCH v4.5 7/8] drm/i915: Introduce per-cgroup display boost setting X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Usually display-boosted contexts get treated as I915_CONTEXT_MAX_USER_PRIORITY+1, which prioritizes them above regular GPU contexts. Now that we allow a much larger range of effective priority values via per-cgroup priority offsets, a system administrator may want more detailed control over how much a process should be boosted by display operations (i.e., can a context from a cgroup with a low priority offset still be display boosted above contexts from a cgroup with a much higher priority offset? or are come cgroups more important than maintaining display rate?). Cc: Chris Wilson Signed-off-by: Matt Roper --- drivers/gpu/drm/i915/i915_cgroup.c | 17 +++++++++++++++++ drivers/gpu/drm/i915/i915_drv.h | 6 ++++++ drivers/gpu/drm/i915/i915_request.h | 1 + drivers/gpu/drm/i915/intel_display.c | 5 +++-- include/uapi/drm/i915_drm.h | 1 + 5 files changed, 28 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cgroup.c b/drivers/gpu/drm/i915/i915_cgroup.c index 0921d624f840..2bef8a5cac93 100644 --- a/drivers/gpu/drm/i915/i915_cgroup.c +++ b/drivers/gpu/drm/i915/i915_cgroup.c @@ -11,6 +11,7 @@ struct i915_cgroup_data { int priority_offset; + int display_boost; struct kref ref; }; @@ -75,6 +76,8 @@ get_or_create_cgroup_data(struct drm_i915_private *dev_priv, goto out; } + priv->display_boost = I915_PRIORITY_DEFAULT_DISPBOOST; + kref_init(&priv->ref); cgroup_priv_install(cgrp, dev_priv->cgroup_priv_key, &priv->ref); @@ -151,6 +154,19 @@ i915_cgroup_setparam_ioctl(struct drm_device *dev, } break; + case I915_CGROUP_PARAM_DISPBOOST_PRIORITY: + if (req->value < I915_PRIORITY_MAX_DISPBOOST && + req->value > I915_PRIORITY_MIN) { + DRM_DEBUG_DRIVER("Setting cgroup display boost priority to %lld\n", + req->value); + cgrpdata->display_boost = req->value; + } else { + DRM_DEBUG_DRIVER("Invalid cgroup display boost priority %lld\n", + req->value); + ret = -EINVAL; + } + break; + default: DRM_DEBUG_DRIVER("Invalid cgroup parameter %lld\n", req->param); ret = -EINVAL; @@ -186,5 +202,6 @@ int i915_cgroup_get_current_##name(struct drm_i915_private *dev_priv) \ } CGROUP_GET(prio_offset, priority_offset, 0) +CGROUP_GET(dispboost, display_boost, I915_PRIORITY_DEFAULT_DISPBOOST); #undef CGROUP_GET diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 72e6cd7bfbae..bde58327b892 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2694,6 +2694,7 @@ int i915_cgroup_setparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file); void i915_cgroup_shutdown(struct drm_i915_private *dev_priv); int i915_cgroup_get_current_prio_offset(struct drm_i915_private *dev_priv); +int i915_cgroup_get_current_dispboost(struct drm_i915_private *dev_priv); #else static inline int i915_cgroup_init(struct drm_i915_private *dev_priv) @@ -2715,6 +2716,11 @@ i915_cgroup_get_current_prio_offset(struct drm_i915_private *dev_priv) { return 0; } +static inline int +i915_cgroup_get_current_dispboost(struct drm_i915_private *dev_priv) +{ + return I915_PRIORITY_DEFAULT_DISPBOOST; +} #endif /* i915_drv.c */ diff --git a/drivers/gpu/drm/i915/i915_request.h b/drivers/gpu/drm/i915/i915_request.h index cf7a7147daf3..db300d93fd08 100644 --- a/drivers/gpu/drm/i915/i915_request.h +++ b/drivers/gpu/drm/i915/i915_request.h @@ -90,6 +90,7 @@ enum { /* Range reachable by combining user priority + cgroup offset */ I915_PRIORITY_MAX = 0x7fffff, I915_PRIORITY_MIN = -I915_PRIORITY_MAX, + I915_PRIORITY_MAX_DISPBOOST = I915_PRIORITY_MAX + 1, /* Special case priority values */ I915_PRIORITY_INVALID = INT_MIN, diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index b053a21f682b..1d0245e2fd75 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -12731,7 +12731,7 @@ intel_prepare_plane_fb(struct drm_plane *plane, struct drm_framebuffer *fb = new_state->fb; struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->state->fb); - int ret; + int boost, ret; if (old_obj) { struct drm_crtc_state *crtc_state = @@ -12783,7 +12783,8 @@ intel_prepare_plane_fb(struct drm_plane *plane, ret = intel_plane_pin_fb(to_intel_plane_state(new_state)); - i915_gem_object_wait_priority(obj, 0, I915_PRIORITY_DEFAULT_DISPBOOST); + boost = i915_cgroup_get_current_dispboost(dev_priv); + i915_gem_object_wait_priority(obj, 0, boost); mutex_unlock(&dev_priv->drm.struct_mutex); i915_gem_object_unpin_pages(obj); diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 6b70f46d224e..ad454f121884 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1727,6 +1727,7 @@ struct drm_i915_cgroup_param { __u32 flags; __u64 param; #define I915_CGROUP_PARAM_PRIORITY_OFFSET 0x1 +#define I915_CGROUP_PARAM_DISPBOOST_PRIORITY 0x2 __s64 value; };