From patchwork Thu Mar 22 21:48:46 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10302391 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2FB8A60386 for ; Thu, 22 Mar 2018 21:52:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2083428534 for ; Thu, 22 Mar 2018 21:52:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 153DC285B6; Thu, 22 Mar 2018 21:52:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id C285F28534 for ; Thu, 22 Mar 2018 21:52:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 197136E0FB; Thu, 22 Mar 2018 21:52:31 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 205646E063 for ; Thu, 22 Mar 2018 21:52:00 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Mar 2018 14:51:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,345,1517904000"; d="scan'208";a="28060221" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga006.jf.intel.com with ESMTP; 22 Mar 2018 14:51:58 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Mar 2018 14:48:46 -0700 Message-Id: <20180322214848.28022-10-jose.souza@intel.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180322214848.28022-1-jose.souza@intel.com> References: <20180322214848.28022-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 10/12] drm/i915/debugfs: Print sink PSR state and debug info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 54 +++++++++++++++++++++++++++++++++++++ 1 file changed, 54 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 16f9977995df..0a0642c61cd0 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2603,6 +2603,44 @@ static const char *psr2_live_status(u32 val) return "unknown"; } +static const char *psr_sink_self_refresh_status(u8 val) +{ + static const char * const sink_status[] = { + "inactive", + "transitioning to active", + "active", + "active receiving selective update", + "transitioning to inactive", + "reserved", + "reserved", + "sink internal error" + }; + + val &= DP_PSR_SINK_STATE_MASK; + if (val < ARRAY_SIZE(sink_status)) + return sink_status[val]; + + return "unknown"; +} + +static void psr_sink_last_received_psr_sdp_sprintf(struct seq_file *m, u32 val) +{ + if (val & DP_PSR_STATE_BIT) + seq_puts(m, "\tPSR active\n"); + if (val & DP_UPDATE_RFB_BIT) + seq_puts(m, "\tUpdate RFB\n"); + if (val & DP_CRC_VALID_BIT) + seq_puts(m, "\tCRC valid\n"); + if (val & DP_SU_VALID) + seq_puts(m, "\tSU valid\n"); + if (val & DP_FIRST_SCAN_LINE_SU_REGION) + seq_puts(m, "\tFirst scan line of the SU region\n"); + if (val & DP_LAST_SCAN_LINE_SU_REGION) + seq_puts(m, "\tLast scan line of the SU region\n"); + if (val & DP_Y_COORDINATE_VALID) + seq_puts(m, "\tY-Coordinate valid\n"); +} + static int i915_edp_psr_status(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2684,6 +2722,22 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n", psr2, psr2_live_status(psr2)); } + + if (dev_priv->psr.enabled) { + struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux; + u8 val; + + if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) == 1) + seq_printf(m, "Sink self refresh status: 0x%x [%s]\n", + val, psr_sink_self_refresh_status(val)); + + if (drm_dp_dpcd_readb(aux, DP_LAST_RECEIVED_PSR_SDP, &val) + == 1) { + seq_printf(m, "Sink last received PSR SDP: 0x%x\n", + val); + psr_sink_last_received_psr_sdp_sprintf(m, val); + } + } mutex_unlock(&dev_priv->psr.lock); intel_runtime_pm_put(dev_priv);