From patchwork Thu Mar 22 21:48:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10302389 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 34C1660216 for ; Thu, 22 Mar 2018 21:52:23 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 25792289AF for ; Thu, 22 Mar 2018 21:52:23 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1A4F028A07; Thu, 22 Mar 2018 21:52:23 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B3DCD289AF for ; Thu, 22 Mar 2018 21:52:22 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 868B76E0A2; Thu, 22 Mar 2018 21:52:21 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2CB456E070 for ; Thu, 22 Mar 2018 21:52:00 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Mar 2018 14:51:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,345,1517904000"; d="scan'208";a="28060223" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga006.jf.intel.com with ESMTP; 22 Mar 2018 14:51:58 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Mar 2018 14:48:47 -0700 Message-Id: <20180322214848.28022-11-jose.souza@intel.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180322214848.28022-1-jose.souza@intel.com> References: <20180322214848.28022-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 11/12] drm/i915/debugfs: Print information about what caused a PSR exit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This will be helpful to debug what hardware is actually tracking. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 47 +++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_reg.h | 18 ++++++++++++++ 2 files changed, 65 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 0a0642c61cd0..3182e9a7cc5d 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2641,6 +2641,43 @@ static void psr_sink_last_received_psr_sdp_sprintf(struct seq_file *m, u32 val) seq_puts(m, "\tY-Coordinate valid\n"); } +static void psr_event_exit_sprintf(struct seq_file *m, u32 val, + bool psr2_enabled) +{ + if (val & EDP_PSR_EVENT_PSR2_WD_TIMER_EXPIRE) + seq_puts(m, "\tPSR2 watchdog timer expired\n"); + if ((val & EDP_PSR_EVENT_PSR2_DISABLED) && psr2_enabled) + seq_puts(m, "\tPSR2 disabled\n"); + if (val & EDP_PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN) + seq_puts(m, "\tSU dirty FIFO underrun\n"); + if (val & EDP_PSR_EVENT_SU_CRC_FIFO_UNDERRUN) + seq_puts(m, "\tSU CRC FIFO underrun\n"); + if (val & EDP_PSR_EVENT_GRAPHICS_RESET) + seq_puts(m, "\tGraphics reset\n"); + if (val & EDP_PSR_EVENT_PCH_INTERRUPT) + seq_puts(m, "\tPCH interrupt\n"); + if (val & EDP_PSR_EVENT_MEMORY_UP) + seq_puts(m, "\tMemory up\n"); + if (val & EDP_PSR_EVENT_FRONT_BUFFER_MODIFY) + seq_puts(m, "\tFront buffer modification\n"); + if (val & EDP_PSR_EVENT_WD_TIMER_EXPIRE) + seq_puts(m, "\tPSR watchdog timer expired\n"); + if (val & EDP_PSR_EVENT_PIPE_REGISTERS_UPDATE) + seq_puts(m, "\tPIPE registers updated\n"); + if (val & EDP_PSR_EVENT_REGISTER_UPDATE) + seq_puts(m, "\tRegister update\n"); + if (val & EDP_PSR_EVENT_HDCP_ENABLE) + seq_puts(m, "\tHDCP enabled\n"); + if (val & EDP_PSR_EVENT_KVMR_SESSION_ENABLE) + seq_puts(m, "\tKVMR session enabled\n"); + if (val & EDP_PSR_EVENT_VBI_ENABLE) + seq_puts(m, "\tVBI enabled\n"); + if (val & EDP_PSR_EVENT_LPSP_MODE_EXIT) + seq_puts(m, "\tLPSP mode exited\n"); + if ((val & EDP_PSR_EVENT_PSR_DISABLE) && !psr2_enabled) + seq_puts(m, "\tPSR disabled\n"); +} + static int i915_edp_psr_status(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2716,6 +2753,16 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) seq_printf(m, "Performance_Counter: %u\n", psrperf); } + + if (INTEL_GEN(dev_priv) >= 9) { + u32 val = I915_READ(EDP_PSR_EVENT); + + seq_printf(m, "Event triggered PSR exit: 0x%x\n", val); + psr_event_exit_sprintf(m, val, dev_priv->psr.psr2_enabled); + /* clean events */ + I915_WRITE(EDP_PSR_EVENT, val); + } + if (dev_priv->psr.psr2_enabled) { u32 psr2 = I915_READ(EDP_PSR2_STATUS); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e660c8a707cf..45f7703a9ee6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3907,6 +3907,24 @@ enum { #define EDP_PSR2_IDLE_FRAME_MASK 0xf #define EDP_PSR2_IDLE_FRAME_SHIFT 0 +#define EDP_PSR_EVENT _MMIO(0x6f848) +#define EDP_PSR_EVENT_PSR2_WD_TIMER_EXPIRE (1 << 17) +#define EDP_PSR_EVENT_PSR2_DISABLED (1 << 16) +#define EDP_PSR_EVENT_SU_DIRTY_FIFO_UNDERRUN (1 << 15) +#define EDP_PSR_EVENT_SU_CRC_FIFO_UNDERRUN (1 << 14) +#define EDP_PSR_EVENT_GRAPHICS_RESET (1 << 12) +#define EDP_PSR_EVENT_PCH_INTERRUPT (1 << 11) +#define EDP_PSR_EVENT_MEMORY_UP (1 << 10) +#define EDP_PSR_EVENT_FRONT_BUFFER_MODIFY (1 << 9) +#define EDP_PSR_EVENT_WD_TIMER_EXPIRE (1 << 8) +#define EDP_PSR_EVENT_PIPE_REGISTERS_UPDATE (1 << 6) +#define EDP_PSR_EVENT_REGISTER_UPDATE (1 << 5) +#define EDP_PSR_EVENT_HDCP_ENABLE (1 << 4) +#define EDP_PSR_EVENT_KVMR_SESSION_ENABLE (1 << 3) +#define EDP_PSR_EVENT_VBI_ENABLE (1 << 2) +#define EDP_PSR_EVENT_LPSP_MODE_EXIT (1 << 1) +#define EDP_PSR_EVENT_PSR_DISABLE (1 << 0) + #define EDP_PSR2_STATUS _MMIO(0x6f940) #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) #define EDP_PSR2_STATUS_STATE_SHIFT 28