From patchwork Thu Mar 22 21:48:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10302385 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9F1FE60386 for ; Thu, 22 Mar 2018 21:52:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 902BE289AF for ; Thu, 22 Mar 2018 21:52:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 84D1328A07; Thu, 22 Mar 2018 21:52:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 04F07289AF for ; Thu, 22 Mar 2018 21:52:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 68F5B6E097; Thu, 22 Mar 2018 21:52:15 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga18.intel.com (mga18.intel.com [134.134.136.126]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B06A6E060 for ; Thu, 22 Mar 2018 21:52:00 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga006.jf.intel.com ([10.7.209.51]) by orsmga106.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 22 Mar 2018 14:51:58 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,345,1517904000"; d="scan'208";a="28060226" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga006.jf.intel.com with ESMTP; 22 Mar 2018 14:51:58 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Thu, 22 Mar 2018 14:48:48 -0700 Message-Id: <20180322214848.28022-12-jose.souza@intel.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180322214848.28022-1-jose.souza@intel.com> References: <20180322214848.28022-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 12/12] drm/i915/debugfs: Print how many blocks were sent in a selective update X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_debugfs.c | 40 ++++++++++++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 17 ++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 3182e9a7cc5d..20985584cc0f 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -2678,6 +2678,43 @@ static void psr_event_exit_sprintf(struct seq_file *m, u32 val, seq_puts(m, "\tPSR disabled\n"); } +static void psr2_su_blocks_sprintf(struct seq_file *m, + struct drm_i915_private *dev_priv) +{ + u32 val; + u16 su; + + val = I915_READ(EDP_PSR2_SU_STATUS); + su = val >> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_SHIFT; + su &= EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N: %d\n", su); + su = val >> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_1_SHIFT; + su &= EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-1: %d\n", su); + su = val >> EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_2_SHIFT; + su &= EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-2: %d\n", su); + + val = I915_READ(EDP_PSR2_SU_STATUS2); + su = val >> EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_3_SHIFT; + su &= EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-3: %d\n", su); + su = val >> EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_4_SHIFT; + su &= EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-4: %d\n", su); + su = val >> EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_5_SHIFT; + su &= EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-5: %d\n", su); + + val = I915_READ(EDP_PSR2_SU_STATUS3); + su = val >> EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_6_SHIFT; + su &= EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-6: %d\n", su); + su = val >> EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_7_SHIFT; + su &= EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_MASK; + seq_printf(m, "\tSU blocks in frame N-7: %d\n", su); +} + static int i915_edp_psr_status(struct seq_file *m, void *data) { struct drm_i915_private *dev_priv = node_to_i915(m->private); @@ -2766,8 +2803,9 @@ static int i915_edp_psr_status(struct seq_file *m, void *data) if (dev_priv->psr.psr2_enabled) { u32 psr2 = I915_READ(EDP_PSR2_STATUS); - seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n", + seq_printf(m, "EDP_PSR2_STATUS: 0x%x [%s]\n", psr2, psr2_live_status(psr2)); + psr2_su_blocks_sprintf(m, dev_priv); } if (dev_priv->psr.enabled) { diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 45f7703a9ee6..18af3e8fd4b6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -3929,6 +3929,23 @@ enum { #define EDP_PSR2_STATUS_STATE_MASK (0xf<<28) #define EDP_PSR2_STATUS_STATE_SHIFT 28 +#define EDP_PSR2_SU_STATUS _MMIO(0x6F914) +#define EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_MASK 0x3FF +#define EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_SHIFT 0 +#define EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_1_SHIFT 10 +#define EDP_PSR2_SU_STATUS_NUM_SU_BLOCKS_FRAME_N_MINUS_2_SHIFT 20 + +#define EDP_PSR2_SU_STATUS2 _MMIO(0x6F918) +#define EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_MASK 0x3FF +#define EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_3_SHIFT 0 +#define EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_4_SHIFT 10 +#define EDP_PSR2_SU_STATUS2_NUM_SU_BLOCKS_FRAME_N_MINUS_5_SHIFT 20 + +#define EDP_PSR2_SU_STATUS3 _MMIO(0x6F91C) +#define EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_MASK 0x3FF +#define EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_6_SHIFT 0 +#define EDP_PSR2_SU_STATUS3_NUM_SU_BLOCKS_FRAME_N_MINUS_7_SHIFT 10 + /* VGA port control */ #define ADPA _MMIO(0x61100) #define PCH_ADPA _MMIO(0xe1100)