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[07/12] drm/i915/psr: Use PSR2 macro for PSR2

Message ID 20180322214848.28022-7-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Souza, Jose March 22, 2018, 9:48 p.m. UTC 
Cosmetic change.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h  | 3 ++-
 drivers/gpu/drm/i915/intel_psr.c | 2 +-
 2 files changed, 3 insertions(+), 2 deletions(-)

Comments

Rodrigo Vivi March 22, 2018, 11:12 p.m. UTC | #1 
On Thu, Mar 22, 2018 at 02:48:43PM -0700, José Roberto de Souza wrote:
> Cosmetic change.
> 
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>


Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>


> ---
>  drivers/gpu/drm/i915/i915_reg.h  | 3 ++-
>  drivers/gpu/drm/i915/intel_psr.c | 2 +-
>  2 files changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 9c4be6bcd1ef..e660c8a707cf 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3903,8 +3903,9 @@ enum {
>  #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
>  #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
>  #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
> -#define   EDP_PSR2_IDLE_MASK		0xf
>  #define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a)<<4)
> +#define   EDP_PSR2_IDLE_FRAME_MASK	0xf
> +#define   EDP_PSR2_IDLE_FRAME_SHIFT	0
>  
>  #define EDP_PSR2_STATUS			_MMIO(0x6f940)
>  #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
> diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
> index f73e2734a859..ad69722c329d 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -331,7 +331,7 @@ static void hsw_activate_psr1(struct intel_dp *intel_dp)
>  	uint32_t val = EDP_PSR_ENABLE;
>  
>  	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
> -	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
> +	val |= idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
>  
>  	if (IS_HASWELL(dev_priv))
>  		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
> -- 
> 2.16.2
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c4be6bcd1ef..e660c8a707cf 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3903,8 +3903,9 @@  enum {
 #define   EDP_PSR2_TP2_TIME_MASK	(3<<8)
 #define   EDP_PSR2_FRAME_BEFORE_SU_SHIFT 4
 #define   EDP_PSR2_FRAME_BEFORE_SU_MASK	(0xf<<4)
-#define   EDP_PSR2_IDLE_MASK		0xf
 #define   EDP_PSR2_FRAME_BEFORE_SU(a)	((a)<<4)
+#define   EDP_PSR2_IDLE_FRAME_MASK	0xf
+#define   EDP_PSR2_IDLE_FRAME_SHIFT	0
 
 #define EDP_PSR2_STATUS			_MMIO(0x6f940)
 #define EDP_PSR2_STATUS_STATE_MASK     (0xf<<28)
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index f73e2734a859..ad69722c329d 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -331,7 +331,7 @@  static void hsw_activate_psr1(struct intel_dp *intel_dp)
 	uint32_t val = EDP_PSR_ENABLE;
 
 	val |= max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT;
-	val |= idle_frames << EDP_PSR_IDLE_FRAME_SHIFT;
+	val |= idle_frames << EDP_PSR2_IDLE_FRAME_SHIFT;
 
 	if (IS_HASWELL(dev_priv))
 		val |= EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;