| Message ID | 20180322214848.28022-9-jose.souza@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Mar 22, 2018 at 02:48:45PM -0700, José Roberto de Souza wrote: > In the 2 eDP1.4a pannels tested set or not set bit have no effect > but is better set it and comply with specification. > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com> > Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> looking at the spec it seems that we never *really* had enabled PSR2! =| Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/intel_psr.c | 12 ++++++------ > 1 file changed, 6 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c > index 19ee6120d3cd..f5c3bcafde25 100644 > --- a/drivers/gpu/drm/i915/intel_psr.c > +++ b/drivers/gpu/drm/i915/intel_psr.c > @@ -278,19 +278,19 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) > struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); > struct drm_device *dev = dig_port->base.base.dev; > struct drm_i915_private *dev_priv = to_i915(dev); > - > + u8 dpcd_val = DP_PSR_ENABLE; > > /* Enable ALPM at sink for psr2 */ > if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm) > drm_dp_dpcd_writeb(&intel_dp->aux, > DP_RECEIVER_ALPM_CONFIG, > DP_ALPM_ENABLE); > + > + if (dev_priv->psr.psr2_enabled) > + dpcd_val |= DP_PSR_ENABLE_PSR2; > if (dev_priv->psr.link_standby) > - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, > - DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); > - else > - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, > - DP_PSR_ENABLE); > + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; > + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); > > drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); > } > -- > 2.16.2 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 19ee6120d3cd..f5c3bcafde25 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -278,19 +278,19 @@ static void hsw_psr_enable_sink(struct intel_dp *intel_dp) struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); - + u8 dpcd_val = DP_PSR_ENABLE; /* Enable ALPM at sink for psr2 */ if (dev_priv->psr.psr2_enabled && dev_priv->psr.alpm) drm_dp_dpcd_writeb(&intel_dp->aux, DP_RECEIVER_ALPM_CONFIG, DP_ALPM_ENABLE); + + if (dev_priv->psr.psr2_enabled) + dpcd_val |= DP_PSR_ENABLE_PSR2; if (dev_priv->psr.link_standby) - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE); - else - drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, - DP_PSR_ENABLE); + dpcd_val |= DP_PSR_MAIN_LINK_ACTIVE; + drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, dpcd_val); drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, DP_SET_POWER_D0); }
In the 2 eDP1.4a pannels tested set or not set bit have no effect but is better set it and comply with specification. Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Cc: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> --- drivers/gpu/drm/i915/intel_psr.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)