From patchwork Fri Mar 23 12:34:08 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: =?utf-8?q?Micha=C5=82_Winiarski?= X-Patchwork-Id: 10304519 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 97AD260385 for ; Fri, 23 Mar 2018 12:35:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8819228E2F for ; Fri, 23 Mar 2018 12:35:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7C49928E35; Fri, 23 Mar 2018 12:35:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DF28028E2F for ; Fri, 23 Mar 2018 12:35:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 565E76E324; Fri, 23 Mar 2018 12:35:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 011236E324 for ; Fri, 23 Mar 2018 12:35:14 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga004.fm.intel.com ([10.253.24.48]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 23 Mar 2018 05:35:14 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,350,1517904000"; d="scan'208";a="39984789" Received: from irsmsx102.ger.corp.intel.com ([163.33.3.155]) by fmsmga004.fm.intel.com with ESMTP; 23 Mar 2018 05:35:12 -0700 Received: from localhost (172.28.172.64) by IRSMSX102.ger.corp.intel.com (163.33.3.155) with Microsoft SMTP Server (TLS) id 14.3.319.2; Fri, 23 Mar 2018 12:35:11 +0000 From: =?UTF-8?q?Micha=C5=82=20Winiarski?= To: Date: Fri, 23 Mar 2018 13:34:08 +0100 Message-ID: <20180323123411.3214-5-michal.winiarski@intel.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180323123411.3214-1-michal.winiarski@intel.com> References: <20180323123411.3214-1-michal.winiarski@intel.com> MIME-Version: 1.0 X-Originating-IP: [172.28.172.64] Subject: [Intel-gfx] [PATCH 5/8] drm/i915/guc: Use GuC FW size and HW restrictions to determine WOPCM partition X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP We need GuC to load HuC, but it's also possible for GuC to operate on its own. We don't know what the size of HuC FW may be, so, not wanting to make any platform-specific hardcoded guesses, we assume that its size is 0... Which is a very bad approximation. This has a very unfortunate consequence - once we've booted with GuC and no HuC, we'll never be able to load HuC (unless we reboot, since the registers are locked). Rather than using unknown values in our computations - let's partition based on GuC size. We have one HW restriction where we're using HuC size (GuC size needs to be roughly similar to HuC size - which may be unknown at this point), luckily, another HW restriction makes it very unlikely to run in any sort of issues in this case. Signed-off-by: Michał Winiarski Cc: Chris Wilson Cc: Jackie Li Cc: Joonas Lahtinen Cc: Michal Wajdeczko --- drivers/gpu/drm/i915/intel_wopcm.c | 60 +++++++++++++++++++++----------------- 1 file changed, 34 insertions(+), 26 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_wopcm.c b/drivers/gpu/drm/i915/intel_wopcm.c index 52841d340002..295d302e97b9 100644 --- a/drivers/gpu/drm/i915/intel_wopcm.c +++ b/drivers/gpu/drm/i915/intel_wopcm.c @@ -167,7 +167,22 @@ static int check_ctx_rsvd_fits(struct intel_wopcm *wopcm, u32 ctx_rsvd) return 0; } -static int wopcm_check_hw_restrictions(struct intel_wopcm *wopcm) +static inline void +__guc_region_grow(struct intel_wopcm *wopcm, u32 size) +{ + /* + * We're growing guc region in the direction of lower addresses. + * We need to use multiples of base alignment, because it has more + * strict alignment rules. + */ + size = DIV_ROUND_UP(size, 2); + size = ALIGN(size, GUC_WOPCM_OFFSET_ALIGNMENT); + + wopcm->guc.base -= size; + wopcm->guc.size += size; +} + +static void wopcm_adjust_for_hw_restrictions(struct intel_wopcm *wopcm) { struct drm_i915_private *i915 = wopcm_to_i915(wopcm); u32 huc_fw_size = intel_uc_fw_get_upload_size(&i915->huc.fw); @@ -177,22 +192,18 @@ static int wopcm_check_hw_restrictions(struct intel_wopcm *wopcm) size = gen9_size_for_dword_gap_restriction(wopcm->guc.base, wopcm->guc.size); if (size) - goto err; + __guc_region_grow(wopcm, size); size = gen9_size_for_huc_restriction(wopcm->guc.size, huc_fw_size); if (size) - goto err; - } - - return 0; + __guc_region_grow(wopcm, size); -err: - DRM_ERROR("GuC WOPCM size %uKiB is too small. %uKiB more needed.\n", - wopcm->guc.size / 1024, - size / 1024); - - return -E2BIG; + GEM_BUG_ON(gen9_size_for_dword_gap_restriction(wopcm->guc.base, + wopcm->guc.size)); + GEM_BUG_ON(gen9_size_for_huc_restriction(wopcm->guc.size, + huc_fw_size)); + } } static bool wopcm_check_components_fit(struct intel_wopcm *wopcm) @@ -218,21 +229,16 @@ static bool wopcm_check_components_fit(struct intel_wopcm *wopcm) return 0; } -static int wopcm_guc_init(struct intel_wopcm *wopcm) +static int wopcm_guc_region_init(struct intel_wopcm *wopcm) { struct drm_i915_private *dev_priv = wopcm_to_i915(wopcm); - u32 huc_fw_size = intel_uc_fw_get_upload_size(&dev_priv->huc.fw); + u32 guc_fw_size = intel_uc_fw_get_upload_size(&dev_priv->guc.fw); u32 ctx_rsvd = context_reserved_size(dev_priv); - wopcm->guc.base = ALIGN_DOWN(huc_fw_size_in_wopcm(huc_fw_size), - GUC_WOPCM_OFFSET_ALIGNMENT); + wopcm->guc.size = guc_fw_size_in_wopcm(guc_fw_size); - wopcm->guc.size = ALIGN(wopcm->size - wopcm->guc.base - ctx_rsvd, - PAGE_SIZE); - - DRM_DEBUG_DRIVER("GuC WOPCM Region: [%uKiB, %uKiB)\n", - wopcm->guc.base / 1024, - (wopcm->guc.base + wopcm->guc.size) / 1024); + wopcm->guc.base = ALIGN_DOWN(wopcm->size - ctx_rsvd - wopcm->guc.size, + GUC_WOPCM_OFFSET_ALIGNMENT); return 0; } @@ -255,18 +261,20 @@ int intel_wopcm_init(struct intel_wopcm *wopcm) GEM_BUG_ON(!wopcm->size); - err = wopcm_guc_init(wopcm); + err = wopcm_guc_region_init(wopcm); if (err) return err; - err = wopcm_check_hw_restrictions(wopcm); - if (err) - return err; + wopcm_adjust_for_hw_restrictions(wopcm); err = wopcm_check_components_fit(wopcm); if (err) return err; + DRM_DEBUG_DRIVER("GuC WOPCM Region: [%uKiB, %uKiB)\n", + wopcm->guc.base / 1024, + (wopcm->guc.base + wopcm->guc.size) / 1024); + return 0; }