| Message ID | 20180323144728.61548-12-michal.wajdeczko@intel.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 3/23/2018 7:47 AM, Michal Wajdeczko wrote: > When running on platform with CTB based GuC communication enabled, > GuC to Host event data will be delivered as CT request message. > However, content of the data[1] of this CT message follows format > of the scratch register used in MMIO based communication, so some > code reuse is still possible. > Spoiler alert, some g2h messages (reset-engine and preemption afaik) will send us more data, so just passing request->data[1] won't be enough ¯\_(ツ)_/¯ > Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> > Cc: Oscar Mateo <oscar.mateo@intel.com> > --- Reviewed-by: Michel Thierry <michel.thierry@intel.com> > drivers/gpu/drm/i915/intel_guc.c | 5 +++++ > drivers/gpu/drm/i915/intel_guc.h | 1 + > drivers/gpu/drm/i915/intel_guc_ct.c | 9 +++++++++ > 3 files changed, 15 insertions(+) > > diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c > index 118db81..b6d2778 100644 > --- a/drivers/gpu/drm/i915/intel_guc.c > +++ b/drivers/gpu/drm/i915/intel_guc.c > @@ -416,6 +416,11 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc) > I915_WRITE(SOFT_SCRATCH(15), val & ~msg); > spin_unlock(&guc->irq_lock); > > + intel_guc_to_host_process_recv_msg(guc, msg); > +} > + > +void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg) > +{ > if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER | > INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) > intel_guc_log_handle_flush_event(&guc->log); > diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h > index 6dc109a..f1265e1 100644 > --- a/drivers/gpu/drm/i915/intel_guc.h > +++ b/drivers/gpu/drm/i915/intel_guc.h > @@ -163,6 +163,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, > void intel_guc_to_host_event_handler(struct intel_guc *guc); > void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); > void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc); > +void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg); > int intel_guc_sample_forcewake(struct intel_guc *guc); > int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); > int intel_guc_suspend(struct intel_guc *guc); > diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c > index 90aff51..9bc8738 100644 > --- a/drivers/gpu/drm/i915/intel_guc_ct.c > +++ b/drivers/gpu/drm/i915/intel_guc_ct.c > @@ -644,8 +644,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) > static void ct_dispatch_request(struct intel_guc_ct *ct, > u32 action, u32 len, const u32 *payload) > { > + struct intel_guc *guc = ct_to_guc(ct); > + > switch (action) { > + case INTEL_GUC_ACTION_DEFAULT: > + if (unlikely(len < 1)) > + goto fail_unexpected; > + intel_guc_to_host_process_recv_msg(guc, *payload); > + break; > + > default: > +fail_unexpected: > DRM_ERROR("CT: unexpected request %x %*phn\n", > action, 4*len, payload); > break; > -- > 1.9.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx >
diff --git a/drivers/gpu/drm/i915/intel_guc.c b/drivers/gpu/drm/i915/intel_guc.c index 118db81..b6d2778 100644 --- a/drivers/gpu/drm/i915/intel_guc.c +++ b/drivers/gpu/drm/i915/intel_guc.c @@ -416,6 +416,11 @@ void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc) I915_WRITE(SOFT_SCRATCH(15), val & ~msg); spin_unlock(&guc->irq_lock); + intel_guc_to_host_process_recv_msg(guc, msg); +} + +void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg) +{ if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER | INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED)) intel_guc_log_handle_flush_event(&guc->log); diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h index 6dc109a..f1265e1 100644 --- a/drivers/gpu/drm/i915/intel_guc.h +++ b/drivers/gpu/drm/i915/intel_guc.h @@ -163,6 +163,7 @@ int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len, void intel_guc_to_host_event_handler(struct intel_guc *guc); void intel_guc_to_host_event_handler_nop(struct intel_guc *guc); void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc); +void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg); int intel_guc_sample_forcewake(struct intel_guc *guc); int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset); int intel_guc_suspend(struct intel_guc *guc); diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c index 90aff51..9bc8738 100644 --- a/drivers/gpu/drm/i915/intel_guc_ct.c +++ b/drivers/gpu/drm/i915/intel_guc_ct.c @@ -644,8 +644,17 @@ static int ct_handle_response(struct intel_guc_ct *ct, const u32 *msg) static void ct_dispatch_request(struct intel_guc_ct *ct, u32 action, u32 len, const u32 *payload) { + struct intel_guc *guc = ct_to_guc(ct); + switch (action) { + case INTEL_GUC_ACTION_DEFAULT: + if (unlikely(len < 1)) + goto fail_unexpected; + intel_guc_to_host_process_recv_msg(guc, *payload); + break; + default: +fail_unexpected: DRM_ERROR("CT: unexpected request %x %*phn\n", action, 4*len, payload); break;
When running on platform with CTB based GuC communication enabled, GuC to Host event data will be delivered as CT request message. However, content of the data[1] of this CT message follows format of the scratch register used in MMIO based communication, so some code reuse is still possible. Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Oscar Mateo <oscar.mateo@intel.com> --- drivers/gpu/drm/i915/intel_guc.c | 5 +++++ drivers/gpu/drm/i915/intel_guc.h | 1 + drivers/gpu/drm/i915/intel_guc_ct.c | 9 +++++++++ 3 files changed, 15 insertions(+)