From patchwork Mon Mar 26 11:50:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10307699 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3D6C760212 for ; Mon, 26 Mar 2018 11:52:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 219212964F for ; Mon, 26 Mar 2018 11:52:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1FFEB2969D; Mon, 26 Mar 2018 11:52:13 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4082829761 for ; Mon, 26 Mar 2018 11:51:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C4CB16E495; Mon, 26 Mar 2018 11:51:22 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id A7DF46E495 for ; Mon, 26 Mar 2018 11:51:20 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11158602-1500050 for multiple; Mon, 26 Mar 2018 12:51:06 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Mon, 26 Mar 2018 12:51:06 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Mon, 26 Mar 2018 12:50:42 +0100 Message-Id: <20180326115044.2505-10-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20180326115044.2505-1-chris@chris-wilson.co.uk> References: <20180326115044.2505-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 09/11] drm/i915/preemption: Select timeout when scheduling X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The choice of preemption timeout is determined by the context from which we trigger the preemption, as such allow the caller to specify the desired timeout. Effectively the other choice would be to use the shortest timeout along the dependency chain. However, given that we would have already triggered preemption for the dependency chain, we can assume that no preemption along that chain is more important than the current request, ergo we need only consider the current timeout. Realising this, we can then pass control of the preemption timeout to the caller for greater flexibility. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_gem.c | 2 +- drivers/gpu/drm/i915/i915_request.c | 2 +- drivers/gpu/drm/i915/intel_lrc.c | 17 ++++++++++------- drivers/gpu/drm/i915/intel_ringbuffer.h | 6 ++++-- 4 files changed, 16 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 038867c96809..675d6bb59337 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -482,7 +482,7 @@ static void __fence_set_priority(struct dma_fence *fence, int prio) rcu_read_lock(); if (engine->schedule) - engine->schedule(rq, prio); + engine->schedule(rq, prio, 0); rcu_read_unlock(); } diff --git a/drivers/gpu/drm/i915/i915_request.c b/drivers/gpu/drm/i915/i915_request.c index 2314a26cd7f8..9d8dcebd9649 100644 --- a/drivers/gpu/drm/i915/i915_request.c +++ b/drivers/gpu/drm/i915/i915_request.c @@ -1102,7 +1102,7 @@ void __i915_request_add(struct i915_request *request, bool flush_caches) */ rcu_read_lock(); if (engine->schedule) - engine->schedule(request, request->ctx->priority); + engine->schedule(request, request->ctx->priority, 0); rcu_read_unlock(); local_bh_disable(); diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 6da816d23cb3..e266657851e1 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1124,17 +1124,19 @@ static void queue_request(struct intel_engine_cs *engine, list_add_tail(&pt->link, &lookup_priolist(engine, pt, prio)->requests); } -static void __submit_queue(struct intel_engine_cs *engine, int prio) +static void __submit_queue(struct intel_engine_cs *engine, + int prio, unsigned int timeout) { engine->execlists.queue_priority = prio; - engine->execlists.queue_preempt_timeout = 0; + engine->execlists.queue_preempt_timeout = timeout; tasklet_hi_schedule(&engine->execlists.tasklet); } -static void submit_queue(struct intel_engine_cs *engine, int prio) +static void submit_queue(struct intel_engine_cs *engine, + int prio, unsigned int timeout) { if (prio > engine->execlists.queue_priority) - __submit_queue(engine, prio); + __submit_queue(engine, prio, timeout); } static void execlists_submit_request(struct i915_request *request) @@ -1146,7 +1148,7 @@ static void execlists_submit_request(struct i915_request *request) spin_lock_irqsave(&engine->timeline->lock, flags); queue_request(engine, &request->priotree, rq_prio(request)); - submit_queue(engine, rq_prio(request)); + submit_queue(engine, rq_prio(request), 0); GEM_BUG_ON(!engine->execlists.first); GEM_BUG_ON(list_empty(&request->priotree.link)); @@ -1174,7 +1176,8 @@ pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) return engine; } -static void execlists_schedule(struct i915_request *request, int prio) +static void execlists_schedule(struct i915_request *request, + int prio, unsigned int timeout) { struct intel_engine_cs *engine; struct i915_dependency *dep, *p; @@ -1270,7 +1273,7 @@ static void execlists_schedule(struct i915_request *request, int prio) if (prio > engine->execlists.queue_priority && i915_sw_fence_done(&pt_to_request(pt)->submit)) - __submit_queue(engine, prio); + __submit_queue(engine, prio, timeout); } spin_unlock_irq(&engine->timeline->lock); diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 7166f47c8489..39df5a39af12 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -467,13 +467,15 @@ struct intel_engine_cs { */ void (*submit_request)(struct i915_request *rq); - /* Call when the priority on a request has changed and it and its + /* + * Call when the priority on a request has changed and it and its * dependencies may need rescheduling. Note the request itself may * not be ready to run! * * Called under the struct_mutex. */ - void (*schedule)(struct i915_request *request, int priority); + void (*schedule)(struct i915_request *request, + int priority, unsigned int timeout); /* * Cancel all requests on the hardware, or queued for execution.