diff mbox

[v2,1/3] drm/i915/icl: read timestamp frequency information

Message ID 20180326133949.12469-2-lionel.g.landwerlin@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Lionel Landwerlin March 26, 2018, 1:39 p.m. UTC 
We're missing this value which is needed for i915/perf support.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h          |  6 ++++
 drivers/gpu/drm/i915/intel_device_info.c | 48 ++++++++++++++++++++++++--------
 2 files changed, 43 insertions(+), 11 deletions(-)
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1bca695f404b..a04348053598 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -861,6 +861,12 @@  static inline bool i915_mmio_reg_valid(i915_reg_t reg)
 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(1 << GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	0
 #define  GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	1
+#define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT	3
+#define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK	(7 << GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT)
+#define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ	0
+#define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ	1
+#define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ	2
+#define  GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ	3
 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT	1
 #define  GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_MASK	(0x3 << GEN10_RPM_CONFIG0_CTC_SHIFT_PARAMETER_SHIFT)
 
diff --git a/drivers/gpu/drm/i915/intel_device_info.c b/drivers/gpu/drm/i915/intel_device_info.c
index 0d1509e25db8..1fa8399eac6c 100644
--- a/drivers/gpu/drm/i915/intel_device_info.c
+++ b/drivers/gpu/drm/i915/intel_device_info.c
@@ -601,6 +601,8 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 	u32 f12_5_mhz = 12500;
 	u32 f19_2_mhz = 19200;
 	u32 f24_mhz = 24000;
+	u32 f38_4_mhz = 38400;
+	u32 f25_mhz = 25000;
 
 	if (INTEL_GEN(dev_priv) <= 4) {
 		/* PRMs say:
@@ -636,7 +638,7 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 		}
 
 		return freq;
-	} else if (INTEL_GEN(dev_priv) <= 10) {
+	} else if (INTEL_GEN(dev_priv) <= 11) {
 		u32 ctc_reg = I915_READ(CTC_MODE);
 		u32 freq = 0;
 		u32 rpm_config_reg = 0;
@@ -652,16 +654,40 @@  static u32 read_timestamp_frequency(struct drm_i915_private *dev_priv)
 			u32 crystal_clock;
 
 			rpm_config_reg = I915_READ(RPM_CONFIG0);
-			crystal_clock = (rpm_config_reg &
-					 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
-				GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
-			switch (crystal_clock) {
-			case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
-				freq = f19_2_mhz;
-				break;
-			case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
-				freq = f24_mhz;
-				break;
+
+			if (INTEL_GEN(dev_priv) == 11) {
+				crystal_clock = (rpm_config_reg &
+						 GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
+					GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+				switch (crystal_clock) {
+				case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
+					freq = f24_mhz;
+					break;
+				case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
+					freq = f19_2_mhz;
+					break;
+				case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_38_4_MHZ:
+					freq = f38_4_mhz;
+					break;
+				case GEN11_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_25_MHZ:
+					freq = f25_mhz;
+					break;
+				default:
+					MISSING_CASE("Invalid frequency setting\n");
+					break;
+				}
+			} else {
+				crystal_clock = (rpm_config_reg &
+						 GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_MASK) >>
+					GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_SHIFT;
+				switch (crystal_clock) {
+				case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_19_2_MHZ:
+					freq = f19_2_mhz;
+					break;
+				case GEN9_RPM_CONFIG0_CRYSTAL_CLOCK_FREQ_24_MHZ:
+					freq = f24_mhz;
+					break;
+				}
 			}
 
 			/* Now figure out how the command stream's timestamp