From patchwork Tue Mar 27 16:40:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10310973 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id F0D9260386 for ; Tue, 27 Mar 2018 16:41:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E00AA28710 for ; Tue, 27 Mar 2018 16:41:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D462E2921B; Tue, 27 Mar 2018 16:41:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DFC0628710 for ; Tue, 27 Mar 2018 16:41:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 369BB6E65C; Tue, 27 Mar 2018 16:41:08 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x242.google.com (mail-wm0-x242.google.com [IPv6:2a00:1450:400c:c09::242]) by gabe.freedesktop.org (Postfix) with ESMTPS id E40BD6E65C for ; Tue, 27 Mar 2018 16:41:05 +0000 (UTC) Received: by mail-wm0-x242.google.com with SMTP id l201so68653wmg.0 for ; Tue, 27 Mar 2018 09:41:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id; bh=SMHn8l0FOWKK/XirnuZHPHbqJkOKdRZohvia7D9jo6s=; b=II7eVaI3/xYgwB/Lhy+bI0SbcuqJlCT4SR1MSJcvEHJ6/rDVFtmjgoeccwdnz/snRx gakSGUFJejarU4qGqR0BLH9J5M6Zd7gzEnhsJSzzPLsw38TYpEYnkiIyBBcJfdAJVHa7 2unWL8nSex8/Twyw+DnlnSC572YrGB6SbbMLU4/bIqE8/Q/RaiONsNx+8PHMVvN5Mjh9 bXJCDI4jYnfLpfOEz0khZ+kdQyIExMIOuoeNmyF57ZfMiK/07KxXhgi5WGzftknf1Ye0 2eL+kXs1D9GJ66h2fzlyvPiN2Qjn0NKIDZgMibAAjnwK9YEpn/D9IaRbvtIAkqVErqbH mjhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=SMHn8l0FOWKK/XirnuZHPHbqJkOKdRZohvia7D9jo6s=; b=aSuMp8svJYL94j3QsGoBLwO67PnRfuGXOQsyoa4xr03MDHy3FLsX4VQWpXE7O6D2p0 b6e3M9RRMTT2B1inOElipvrh9fjsdd8zuA8/Zf+ip/6ixW9BsW9arcPrASfNSk5T/H/C WVAw7LA8YsTA4CnLvPdbrTfmfdyiHOsnw18hZy4LWq0Y7G47/QdtsQ3b9NyeWbFuU3Q3 TO1SNwPp51xT1zEwyxq9Gv4O7u51r73gfBVauWPTkYeYWV2ke6eyFUXaeELGdcjq7tTi AesPfdv906No0RHql1YQ3TvJd4FWjUl6FOPG5Veue5J7Ie6AkN7AQY7eu8Pd796XjTdB hMRQ== X-Gm-Message-State: AElRT7GoQn5+b6xnjiXbTUwiJMvznPNFHYqSs2yNBZq4LWlK4Q81szA4 3MOtwu3Wpoy+cHfwuvkFm/7BpQ== X-Google-Smtp-Source: AIpwx48/oIjQtbqB4oHhzSRMGEPUgM4OoQY57hjj5Lh8yQMFl1uQjheO4nzM7+af6wXG1X+58ClO/g== X-Received: by 10.28.54.88 with SMTP id d85mr27583wma.2.1522168864454; Tue, 27 Mar 2018 09:41:04 -0700 (PDT) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id y30sm1980080wrd.83.2018.03.27.09.41.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Tue, 27 Mar 2018 09:41:03 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: igt-dev@lists.freedesktop.org Date: Tue, 27 Mar 2018 17:40:56 +0100 Message-Id: <20180327164056.6301-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 Subject: [Intel-gfx] [PATCH i-g-t] tests/gem_eio: Never re-use contexts which were in the middle of GPU reset X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Intel-gfx@lists.freedesktop.org MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Contexts executing when reset triggers are potentialy corrupt so trying to use them from a subsequent test (like the default context) can hang the GPU or even the driver. Workaround that by always creating a dedicated context which will be running when GPU reset happens. Signed-off-by: Tvrtko Ursulin --- tests/gem_eio.c | 96 +++++++++++++++++++++++++++++++++++---------------------- 1 file changed, 60 insertions(+), 36 deletions(-) diff --git a/tests/gem_eio.c b/tests/gem_eio.c index b824d9d4c9c0..cefe26adf893 100644 --- a/tests/gem_eio.c +++ b/tests/gem_eio.c @@ -249,14 +249,34 @@ static int __check_wait(int fd, uint32_t bo, unsigned int wait) return ret; } +static uint32_t context_create_safe(int i915) +{ + struct drm_i915_gem_context_param param; + + memset(¶m, 0, sizeof(param)); + + param.ctx_id = gem_context_create(i915); + param.param = I915_CONTEXT_PARAM_BANNABLE; + gem_context_set_param(i915, ¶m); + + param.param = I915_CONTEXT_PARAM_NO_ERROR_CAPTURE; + param.value = 1; + gem_context_set_param(i915, ¶m); + + return param.ctx_id; +} + #define TEST_WEDGE (1) static void test_wait(int fd, unsigned int flags, unsigned int wait) { igt_spin_t *hang; + uint32_t ctx; igt_require_gem(fd); + ctx = context_create_safe(fd); + /* * If the request we wait on completes due to a hang (even for * that request), the user expects the return value to 0 (success). @@ -267,7 +287,7 @@ static void test_wait(int fd, unsigned int flags, unsigned int wait) else igt_require(i915_reset_control(true)); - hang = spin_sync(fd, 0, I915_EXEC_DEFAULT); + hang = spin_sync(fd, ctx, I915_EXEC_DEFAULT); igt_assert_eq(__check_wait(fd, hang->handle, wait), 0); @@ -276,6 +296,8 @@ static void test_wait(int fd, unsigned int flags, unsigned int wait) igt_require(i915_reset_control(true)); trigger_reset(fd); + + gem_context_destroy(fd, ctx); } static void test_suspend(int fd, int state) @@ -309,6 +331,7 @@ static void test_inflight(int fd, unsigned int wait) for_each_engine(fd, engine) { struct drm_i915_gem_execbuffer2 execbuf; + uint32_t ctx = context_create_safe(fd); igt_spin_t *hang; int fence[64]; /* conservative estimate of ring size */ @@ -316,7 +339,7 @@ static void test_inflight(int fd, unsigned int wait) igt_debug("Starting %s on engine '%s'\n", __func__, e__->name); igt_require(i915_reset_control(false)); - hang = spin_sync(fd, 0, engine); + hang = spin_sync(fd, ctx, engine); obj[0].handle = hang->handle; memset(&execbuf, 0, sizeof(execbuf)); @@ -340,6 +363,8 @@ static void test_inflight(int fd, unsigned int wait) igt_spin_batch_free(fd, hang); igt_assert(i915_reset_control(true)); trigger_reset(fd); + + gem_context_destroy(fd, ctx); } } @@ -350,17 +375,20 @@ static void test_inflight_suspend(int fd) uint32_t bbe = MI_BATCH_BUFFER_END; int fence[64]; /* conservative estimate of ring size */ igt_spin_t *hang; + uint32_t ctx; igt_require_gem(fd); igt_require(gem_has_exec_fence(fd)); igt_require(i915_reset_control(false)); + ctx = context_create_safe(fd); + memset(obj, 0, sizeof(obj)); obj[0].flags = EXEC_OBJECT_WRITE; obj[1].handle = gem_create(fd, 4096); gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe)); - hang = spin_sync(fd, 0, 0); + hang = spin_sync(fd, ctx, 0); obj[0].handle = hang->handle; memset(&execbuf, 0, sizeof(execbuf)); @@ -387,23 +415,8 @@ static void test_inflight_suspend(int fd) igt_spin_batch_free(fd, hang); igt_assert(i915_reset_control(true)); trigger_reset(fd); -} - -static uint32_t context_create_safe(int i915) -{ - struct drm_i915_gem_context_param param; - - memset(¶m, 0, sizeof(param)); - param.ctx_id = gem_context_create(i915); - param.param = I915_CONTEXT_PARAM_BANNABLE; - gem_context_set_param(i915, ¶m); - - param.param = I915_CONTEXT_PARAM_NO_ERROR_CAPTURE; - param.value = 1; - gem_context_set_param(i915, ¶m); - - return param.ctx_id; + gem_context_destroy(fd, ctx); } static void test_inflight_contexts(int fd, unsigned int wait) @@ -411,40 +424,40 @@ static void test_inflight_contexts(int fd, unsigned int wait) struct drm_i915_gem_exec_object2 obj[2]; const uint32_t bbe = MI_BATCH_BUFFER_END; unsigned int engine; - uint32_t ctx[64]; + uint32_t ctx[65]; igt_require_gem(fd); igt_require(gem_has_exec_fence(fd)); gem_require_contexts(fd); - for (unsigned int n = 0; n < ARRAY_SIZE(ctx); n++) - ctx[n] = context_create_safe(fd); - memset(obj, 0, sizeof(obj)); obj[0].flags = EXEC_OBJECT_WRITE; obj[1].handle = gem_create(fd, 4096); gem_write(fd, obj[1].handle, 0, &bbe, sizeof(bbe)); for_each_engine(fd, engine) { - struct drm_i915_gem_execbuffer2 execbuf; + struct drm_i915_gem_execbuffer2 execbuf = { }; igt_spin_t *hang; int fence[64]; - gem_quiescent_gpu(fd); - igt_debug("Starting %s on engine '%s'\n", __func__, e__->name); + igt_require(i915_reset_control(false)); - hang = spin_sync(fd, 0, engine); + for (unsigned int n = 0; n < ARRAY_SIZE(ctx); n++) + ctx[n] = context_create_safe(fd); + + gem_quiescent_gpu(fd); + + hang = spin_sync(fd, ctx[0], engine); obj[0].handle = hang->handle; - memset(&execbuf, 0, sizeof(execbuf)); execbuf.buffers_ptr = to_user_pointer(obj); execbuf.buffer_count = 2; execbuf.flags = engine | I915_EXEC_FENCE_OUT; - for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) { - execbuf.rsvd1 = ctx[n]; + for (unsigned int n = 0; n < (ARRAY_SIZE(fence) - 1); n++) { + execbuf.rsvd1 = ctx[n + 1]; gem_execbuf_wr(fd, &execbuf); fence[n] = execbuf.rsvd2 >> 32; igt_assert(fence[n] != -1); @@ -452,18 +465,19 @@ static void test_inflight_contexts(int fd, unsigned int wait) igt_assert_eq(__check_wait(fd, obj[1].handle, wait), 0); - for (unsigned int n = 0; n < ARRAY_SIZE(fence); n++) { + for (unsigned int n = 0; n < (ARRAY_SIZE(fence) - 1); n++) { igt_assert_eq(sync_fence_status(fence[n]), -EIO); close(fence[n]); } igt_spin_batch_free(fd, hang); + + for (unsigned int n = 0; n < ARRAY_SIZE(ctx); n++) + gem_context_destroy(fd, ctx[n]); + igt_assert(i915_reset_control(true)); trigger_reset(fd); } - - for (unsigned int n = 0; n < ARRAY_SIZE(ctx); n++) - gem_context_destroy(fd, ctx[n]); } static void test_inflight_external(int fd) @@ -473,15 +487,18 @@ static void test_inflight_external(int fd) struct drm_i915_gem_exec_object2 obj; igt_spin_t *hang; uint32_t fence; + uint32_t ctx; IGT_CORK_FENCE(cork); igt_require_sw_sync(); igt_require(gem_has_exec_fence(fd)); + ctx = context_create_safe(fd); + fence = igt_cork_plug(&cork, fd); igt_require(i915_reset_control(false)); - hang = __spin_poll(fd, 0, 0); + hang = __spin_poll(fd, ctx, 0); memset(&obj, 0, sizeof(obj)); obj.handle = gem_create(fd, 4096); @@ -514,6 +531,8 @@ static void test_inflight_external(int fd) igt_spin_batch_free(fd, hang); igt_assert(i915_reset_control(true)); trigger_reset(fd); + + gem_context_destroy(fd, ctx); } static void test_inflight_internal(int fd, unsigned int wait) @@ -524,12 +543,15 @@ static void test_inflight_internal(int fd, unsigned int wait) unsigned engine, nfence = 0; int fences[16]; igt_spin_t *hang; + uint32_t ctx; igt_require_gem(fd); igt_require(gem_has_exec_fence(fd)); + ctx = context_create_safe(fd); + igt_require(i915_reset_control(false)); - hang = spin_sync(fd, 0, 0); + hang = spin_sync(fd, ctx, 0); memset(obj, 0, sizeof(obj)); obj[0].handle = hang->handle; @@ -560,6 +582,8 @@ static void test_inflight_internal(int fd, unsigned int wait) igt_spin_batch_free(fd, hang); igt_assert(i915_reset_control(true)); trigger_reset(fd); + + gem_context_destroy(fd, ctx); } static int fd = -1;