From patchwork Fri Mar 30 22:23:28 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10318463 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C5B24602D6 for ; Fri, 30 Mar 2018 22:27:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A02F128606 for ; Fri, 30 Mar 2018 22:27:33 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 92720286EE; Fri, 30 Mar 2018 22:27:33 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 24EC228606 for ; Fri, 30 Mar 2018 22:27:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 906216E963; Fri, 30 Mar 2018 22:27:32 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 9D1106E444 for ; Fri, 30 Mar 2018 22:26:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 15:26:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,383,1517904000"; d="scan'208";a="39551580" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga003.jf.intel.com with ESMTP; 30 Mar 2018 15:26:53 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 15:23:28 -0700 Message-Id: <20180330222336.5262-3-jose.souza@intel.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20180330222336.5262-1-jose.souza@intel.com> References: <20180330222336.5262-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 03/11] drm/i915/psr: Share code between disable and exit X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP The disable and exit sequence are very similar with a lot common code between both, so here sharing the code. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 2 +- drivers/gpu/drm/i915/intel_psr.c | 84 ++++++++++++++++++---------------------- 2 files changed, 38 insertions(+), 48 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index a8d300280a2c..cb72ee27422f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -617,7 +617,7 @@ struct i915_psr { void (*enable_sink)(struct intel_dp *); void (*activate)(struct intel_dp *); void (*setup_vsc)(struct intel_dp *, const struct intel_crtc_state *); - void (*exit)(struct intel_dp *intel_dp); + void (*exit)(struct intel_dp *intel_dp, bool disabling); }; enum intel_pch { diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index bcaac9e69f8c..d3451afeb8bb 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -672,23 +672,9 @@ static void vlv_psr_disable(struct intel_dp *intel_dp, struct drm_device *dev = intel_dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); - uint32_t val; if (dev_priv->psr.active) { - /* Put VLV PSR back to PSR_state 0 (disabled). */ - if (intel_wait_for_register(dev_priv, - VLV_PSRSTAT(crtc->pipe), - VLV_EDP_PSR_IN_TRANS, - 0, - 1)) - WARN(1, "PSR transition took longer than expected\n"); - - val = I915_READ(VLV_PSRCTL(crtc->pipe)); - val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; - val &= ~VLV_EDP_PSR_ENABLE; - val &= ~VLV_EDP_PSR_MODE_MASK; - I915_WRITE(VLV_PSRCTL(crtc->pipe), val); - + dev_priv->psr.exit(intel_dp, true); dev_priv->psr.active = false; } else { WARN_ON(vlv_is_psr_active_on_pipe(dev, crtc->pipe)); @@ -703,31 +689,7 @@ static void hsw_psr_disable(struct intel_dp *intel_dp, struct drm_i915_private *dev_priv = to_i915(dev); if (dev_priv->psr.active) { - i915_reg_t psr_status; - u32 psr_status_mask; - - if (dev_priv->psr.psr2_enabled) { - psr_status = EDP_PSR2_STATUS; - psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; - - I915_WRITE(EDP_PSR2_CTL, - I915_READ(EDP_PSR2_CTL) & - ~(EDP_PSR2_ENABLE | EDP_SU_TRACK_ENABLE)); - - } else { - psr_status = EDP_PSR_STATUS; - psr_status_mask = EDP_PSR_STATUS_STATE_MASK; - - I915_WRITE(EDP_PSR_CTL, - I915_READ(EDP_PSR_CTL) & ~EDP_PSR_ENABLE); - } - - /* Wait till PSR is idle */ - if (intel_wait_for_register(dev_priv, - psr_status, psr_status_mask, 0, - 2000)) - DRM_ERROR("Timed out waiting for PSR Idle State\n"); - + dev_priv->psr.exit(intel_dp, true); dev_priv->psr.active = false; } else { if (dev_priv->psr.psr2_enabled) @@ -838,25 +800,41 @@ static void intel_psr_work(struct work_struct *work) mutex_unlock(&dev_priv->psr.lock); } -static void hsw_psr_exit(struct intel_dp *intel_dp) +static void hsw_psr_exit(struct intel_dp *intel_dp, bool disabling) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; struct drm_i915_private *dev_priv = to_i915(dev); + i915_reg_t psr_status; + u32 psr_status_mask; u32 val; if (dev_priv->psr.psr2_enabled) { + psr_status = EDP_PSR2_STATUS; + psr_status_mask = EDP_PSR2_STATUS_STATE_MASK; + val = I915_READ(EDP_PSR2_CTL); - WARN_ON(!(val & EDP_PSR2_ENABLE)); - I915_WRITE(EDP_PSR2_CTL, val & ~EDP_PSR2_ENABLE); + WARN_ON(!disabling && !(val & EDP_PSR2_ENABLE)); + val &= ~EDP_PSR2_ENABLE; + if (disabling) + val &= ~EDP_SU_TRACK_ENABLE; + I915_WRITE(EDP_PSR2_CTL, val); } else { + psr_status = EDP_PSR_STATUS; + psr_status_mask = EDP_PSR_STATUS_STATE_MASK; + val = I915_READ(EDP_PSR_CTL); - WARN_ON(!(val & EDP_PSR_ENABLE)); + WARN_ON(!disabling && !(val & EDP_PSR_ENABLE)); I915_WRITE(EDP_PSR_CTL, val & ~EDP_PSR_ENABLE); } + + /* When disabling wait till PSR is idle */ + if (disabling && intel_wait_for_register(dev_priv, psr_status, + psr_status_mask, 0, 2000)) + DRM_ERROR("Timed out waiting for PSR Idle State\n"); } -static void vlv_psr_exit(struct intel_dp *intel_dp) +static void vlv_psr_exit(struct intel_dp *intel_dp, bool disabling) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = dig_port->base.base.dev; @@ -865,10 +843,14 @@ static void vlv_psr_exit(struct intel_dp *intel_dp) enum pipe pipe = to_intel_crtc(crtc)->pipe; u32 val; + if (disabling && intel_wait_for_register(dev_priv, VLV_PSRSTAT(pipe), + VLV_EDP_PSR_IN_TRANS, 0, 1)) + DRM_WARN("PSR transition took longer than expected\n"); + val = I915_READ(VLV_PSRCTL(pipe)); /* - * Here we do the transition drirectly from + * Here we do the transition directly from * PSR_state 3 (active - no Remote Frame Buffer (RFB) update) to * PSR_state 5 (exit). * PSR State 4 (active with single frame update) can be skipped. @@ -877,8 +859,16 @@ static void vlv_psr_exit(struct intel_dp *intel_dp) * Now we are at Same state after vlv_psr_enable_source. */ val &= ~VLV_EDP_PSR_ACTIVE_ENTRY; + if (disabling) { + /* Put VLV PSR back to PSR_state 0 (disabled). */ + val &= ~VLV_EDP_PSR_ENABLE; + val &= ~VLV_EDP_PSR_MODE_MASK; + } I915_WRITE(VLV_PSRCTL(pipe), val); + if (disabling) + return; + /* * Send AUX wake up - Spec says after transitioning to PSR * active we have to send AUX wake up by writing 01h in DPCD @@ -898,7 +888,7 @@ static void intel_psr_exit(struct drm_i915_private *dev_priv) if (!dev_priv->psr.active) return; - dev_priv->psr.exit(intel_dp); + dev_priv->psr.exit(intel_dp, false); dev_priv->psr.active = false; }