From patchwork Fri Mar 30 22:23:30 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10318455 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 2BB2A602D6 for ; Fri, 30 Mar 2018 22:27:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0FFE52A657 for ; Fri, 30 Mar 2018 22:27:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 0497B2A672; Fri, 30 Mar 2018 22:27:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8EC662A663 for ; Fri, 30 Mar 2018 22:27:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 1DAB36E947; Fri, 30 Mar 2018 22:27:16 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 92E046E441 for ; Fri, 30 Mar 2018 22:26:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 15:26:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,383,1517904000"; d="scan'208";a="39551586" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga003.jf.intel.com with ESMTP; 30 Mar 2018 15:26:54 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 15:23:30 -0700 Message-Id: <20180330222336.5262-5-jose.souza@intel.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20180330222336.5262-1-jose.souza@intel.com> References: <20180330222336.5262-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 05/11] drm/i915/psr: Export intel_psr_activate/exit() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Export this functions so other modules can activate and exit PSR. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/intel_drv.h | 2 + drivers/gpu/drm/i915/intel_psr.c | 94 +++++++++++++++++++++++++++++++++++++--- 2 files changed, 89 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index d1452fd2a58d..70026b772721 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1891,6 +1891,8 @@ void intel_psr_single_frame_update(struct drm_i915_private *dev_priv, unsigned frontbuffer_bits); void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_idle); +void intel_psr_activate(struct intel_dp *intel_dp, bool schedule); /* intel_runtime_pm.c */ int intel_power_domains_init(struct drm_i915_private *); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index c4720b0152c3..906a12ea934d 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -56,6 +56,8 @@ #include "intel_drv.h" #include "i915_drv.h" +#define ACTIVATE_WORK_MSEC_DELAY 100 + static inline enum intel_display_power_domain psr_aux_domain(struct intel_dp *intel_dp) { @@ -548,7 +550,7 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, DRM_DEBUG_KMS("Enabling PSR%s\n", crtc_state->has_psr2 ? "2" : ""); } -static void intel_psr_activate(struct intel_dp *intel_dp) +static void __intel_psr_activate(struct intel_dp *intel_dp) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_device *dev = intel_dig_port->base.base.dev; @@ -645,7 +647,7 @@ void intel_psr_enable(struct intel_dp *intel_dp, dev_priv->psr.enabled = intel_dp; if (INTEL_GEN(dev_priv) >= 9) { - intel_psr_activate(intel_dp); + __intel_psr_activate(intel_dp); } else { /* * FIXME: Activation should happen immediately since this @@ -794,7 +796,7 @@ static void intel_psr_work(struct work_struct *work) if (dev_priv->psr.busy_frontbuffer_bits) goto unlock; - intel_psr_activate(intel_dp); + __intel_psr_activate(intel_dp); unlock: mutex_unlock(&dev_priv->psr.lock); } @@ -880,7 +882,7 @@ static void vlv_psr_exit(struct intel_dp *intel_dp, bool disabling) DP_SET_POWER_D0); } -static void intel_psr_exit(struct drm_i915_private *dev_priv) +static void __intel_psr_exit(struct drm_i915_private *dev_priv) { struct intel_dp *intel_dp = dev_priv->psr.enabled; @@ -977,7 +979,7 @@ void intel_psr_invalidate(struct drm_i915_private *dev_priv, dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits; if (frontbuffer_bits) - intel_psr_exit(dev_priv); + __intel_psr_exit(dev_priv); mutex_unlock(&dev_priv->psr.lock); } @@ -1023,7 +1025,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, if (frontbuffer_bits) { if (dev_priv->psr.psr2_enabled || IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { - intel_psr_exit(dev_priv); + __intel_psr_exit(dev_priv); } else { /* * Display WA #0884: all @@ -1041,7 +1043,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv, if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits) if (!work_busy(&dev_priv->psr.work.work)) schedule_delayed_work(&dev_priv->psr.work, - msecs_to_jiffies(100)); + msecs_to_jiffies(ACTIVATE_WORK_MSEC_DELAY)); mutex_unlock(&dev_priv->psr.lock); } @@ -1108,3 +1110,81 @@ void intel_psr_init(struct drm_i915_private *dev_priv) dev_priv->psr.exit = hsw_psr_exit; } } + +/** + * intel_psr_exit - Exit PSR + * @intel_dp: DisplayPort that should have PSR exited if active + * @wait_idle: if true wait until PSR is inactive otherwise just request it + * + * This function exit PSR if enabled and active in this DisplayPort. + */ +void intel_psr_exit(struct intel_dp *intel_dp, bool wait_idle) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + if (!CAN_PSR(dev_priv)) + return; + + mutex_lock(&dev_priv->psr.lock); + if (dev_priv->psr.enabled != intel_dp) + goto out; + if (!dev_priv->psr.active && !wait_idle) + goto out; + + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { + struct drm_crtc *crtc = dig_port->base.base.crtc; + enum pipe pipe = to_intel_crtc(crtc)->pipe; + + __intel_psr_exit(dev_priv); + + if (!wait_idle) + goto out; + + if (intel_wait_for_register(dev_priv, VLV_PSRSTAT(pipe), + VLV_EDP_PSR_IN_TRANS, 0, 2000)) + DRM_ERROR("Timed out waiting for PSR Idle State\n"); + } else { + /* HSW+ PSR disable is actually, exit + wait transition */ + dev_priv->psr.exit(intel_dp, wait_idle); + dev_priv->psr.active = false; + } + +out: + mutex_unlock(&dev_priv->psr.lock); +} + +/** + * intel_psr_activate - Activate PSR + * @intel_dp: DisplayPort that should have PSR activated if enabled + * @schedule: if true schedule the active to happens in a few milliseconds + * otherwise activate right now. + * + * This function activate PSR if enabled in this DisplayPort. + */ +void intel_psr_activate(struct intel_dp *intel_dp, bool schedule) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + if (!CAN_PSR(dev_priv)) + return; + + mutex_lock(&dev_priv->psr.lock); + if (dev_priv->psr.enabled != intel_dp || dev_priv->psr.active) + goto out; + + if (dev_priv->psr.busy_frontbuffer_bits) + goto out; + + if (schedule) { + if (!work_busy(&dev_priv->psr.work.work)) + schedule_delayed_work(&dev_priv->psr.work, + msecs_to_jiffies(ACTIVATE_WORK_MSEC_DELAY)); + } else + __intel_psr_activate(intel_dp); +out: + mutex_unlock(&dev_priv->psr.lock); +}