From patchwork Fri Mar 30 22:23:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10318449 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E27D5602D6 for ; Fri, 30 Mar 2018 22:27:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C72432A657 for ; Fri, 30 Mar 2018 22:27:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BBB922A672; Fri, 30 Mar 2018 22:27:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 645502A657 for ; Fri, 30 Mar 2018 22:27:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 17BBA6E46D; Fri, 30 Mar 2018 22:27:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id ADF936E005 for ; Fri, 30 Mar 2018 22:26:56 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 30 Mar 2018 15:26:54 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,383,1517904000"; d="scan'208";a="39551590" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga003.jf.intel.com with ESMTP; 30 Mar 2018 15:26:54 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 30 Mar 2018 15:23:31 -0700 Message-Id: <20180330222336.5262-6-jose.souza@intel.com> X-Mailer: git-send-email 2.16.3 In-Reply-To: <20180330222336.5262-1-jose.souza@intel.com> References: <20180330222336.5262-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 06/11] drm/i915/psr: Add intel_psr_activate_block_get()/put() X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan , Rodrigo Vivi Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP intel_psr_activate_block_get() should be called when by some reason PSR should not be activated for some time, it will increment counter and it should the decremented by intel_psr_activate_block_put() when PSR can be activated again. intel_psr_activate_block_put() will not actually activate PSR, users of this function should also call intel_psr_activate(). Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan Cc: Rodrigo Vivi --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/intel_drv.h | 2 ++ drivers/gpu/drm/i915/intel_psr.c | 54 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 57 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 99af9169d792..41ebb144594e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -609,6 +609,7 @@ struct i915_psr { bool has_hw_tracking; bool psr2_enabled; u8 sink_sync_latency; + unsigned int activate_block_count; void (*enable_source)(struct intel_dp *, const struct intel_crtc_state *); diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h index 70026b772721..020b96324135 100644 --- a/drivers/gpu/drm/i915/intel_drv.h +++ b/drivers/gpu/drm/i915/intel_drv.h @@ -1893,6 +1893,8 @@ void intel_psr_compute_config(struct intel_dp *intel_dp, struct intel_crtc_state *crtc_state); void intel_psr_exit(struct intel_dp *intel_dp, bool wait_idle); void intel_psr_activate(struct intel_dp *intel_dp, bool schedule); +void intel_psr_activate_block_get(struct intel_dp *intel_dp); +void intel_psr_activate_block_put(struct intel_dp *intel_dp); /* intel_runtime_pm.c */ int intel_power_domains_init(struct drm_i915_private *); diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c index 906a12ea934d..8702dbafb42d 100644 --- a/drivers/gpu/drm/i915/intel_psr.c +++ b/drivers/gpu/drm/i915/intel_psr.c @@ -558,6 +558,8 @@ static void __intel_psr_activate(struct intel_dp *intel_dp) WARN_ON(dev_priv->psr.active); lockdep_assert_held(&dev_priv->psr.lock); + if (dev_priv->psr.activate_block_count) + return; dev_priv->psr.activate(intel_dp); dev_priv->psr.active = true; @@ -1188,3 +1190,55 @@ void intel_psr_activate(struct intel_dp *intel_dp, bool schedule) out: mutex_unlock(&dev_priv->psr.lock); } + +/** + * intel_psr_activate_block_get - Block further attempts to activate PSR + * @intel_dp: DisplayPort that have PSR enabled + * + * It have a internal reference count, so each intel_psr_activate_block_get() + * should have a intel_psr_activate_block_put() counterpart. + */ +void intel_psr_activate_block_get(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + if (!CAN_PSR(dev_priv)) + return; + + mutex_lock(&dev_priv->psr.lock); + if (dev_priv->psr.enabled != intel_dp) + goto out; + + dev_priv->psr.activate_block_count++; +out: + mutex_unlock(&dev_priv->psr.lock); +} + + +/** + * intel_psr_activate_block_put - Unblock further attempts to activate PSR + * @intel_dp: DisplayPort that have PSR enabled + * + * Decrease the reference counter incremented by intel_psr_activate_block_get() + * when zero it allows PSR be activate. To actually activate PSR when reference + * counter is zero intel_psr_activate() should be called. + */ +void intel_psr_activate_block_put(struct intel_dp *intel_dp) +{ + struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); + struct drm_device *dev = dig_port->base.base.dev; + struct drm_i915_private *dev_priv = to_i915(dev); + + if (!CAN_PSR(dev_priv)) + return; + + mutex_lock(&dev_priv->psr.lock); + if (dev_priv->psr.enabled != intel_dp) + goto out; + + dev_priv->psr.activate_block_count--; +out: + mutex_unlock(&dev_priv->psr.lock); +}