From patchwork Thu Apr 5 12:39:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10324517 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 452CF6053F for ; Thu, 5 Apr 2018 12:39:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 34DA029181 for ; Thu, 5 Apr 2018 12:39:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2977129184; Thu, 5 Apr 2018 12:39:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B3FDF29181 for ; Thu, 5 Apr 2018 12:39:42 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E2A76E768; Thu, 5 Apr 2018 12:39:41 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wm0-x241.google.com (mail-wm0-x241.google.com [IPv6:2a00:1450:400c:c09::241]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2FA3C6E760 for ; Thu, 5 Apr 2018 12:39:38 +0000 (UTC) Received: by mail-wm0-x241.google.com with SMTP id u189so5302727wmd.1 for ; Thu, 05 Apr 2018 05:39:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Z3jumR2YWcGlmbyXIU03nkVcOWPv/RPXU4pZ7/lnH+4=; b=Uk6ePuABD2ZBRgN7+ohwhkVP7ZT4SWMWTzhTL03a0DFlynCtmxtu/MjzeGM20FMgV9 NlL6+QVECnNbVqLLaaXlo0TQ1Tyl5/BkOhnSCUNH/161REY6ddCLKcgjX/bYFWG+P1LR hC/6psdqCJNp65xeu0WdpuSKa0TiQTEJ5V/k90j30OKms/8ukx2vunJY3krTujGeTV/F XNU/6/JruGh6ASqSf+b/BLyam80fnGbDLjkIGCjxr7w+7dSeVnI7cse5gfVss5WaWMTD nylW3L6F7LKYaOWcwfNZXkAoUxabejhL7UNSk/bFvFsMXaQ6liT1Ik9dX8Yl7zLyaitV orJg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Z3jumR2YWcGlmbyXIU03nkVcOWPv/RPXU4pZ7/lnH+4=; b=mYoo4zk6Oyx7TChCU9HpDlKQCJ6/mww0ODlQEL/1lzxrxW5wYdjE/NVP1uhQaA4dUu 0pUDy5DSUXghKQIqH6byBtOc0/y6HcyE6HpFNyUO8TaeL+8nK4cC+RdNUKWpZqq97JJ2 /G/fCJaQOlEGm+dbi1dkKGFkKKjCkJBYtBlmH65esBsG7v2IszIjoY5EXssz7bv+xQ3P btnjjG56dSZCvrsVdwIZPkU2msByn6Nh6gt1a7G6M0XtjBalLg6ZNlt2Ugw4eJ6JWB7f Lr8ktLh+VbicwgNjygWOnbDBu1pYPR3P4Exw81Y2xdPrYnyx+k9GQ5p3KMmJCulw+QY1 R4KA== X-Gm-Message-State: AElRT7HvgGDyBb/yG5jPX6bMy4kr+9bp0v4557txbxkLQKZHoNWEVkKo ghVqQzkATqALkOs9AzZwhzmYqyvt X-Google-Smtp-Source: AIpwx4/2S99cB3C8CO6im9X+ycOspsu1zvMxzBCuajhvWw9b77NfMnbcFBZTvuRPn34G5ET3TAyv0A== X-Received: by 10.28.35.76 with SMTP id j73mr9392043wmj.103.1522931976630; Thu, 05 Apr 2018 05:39:36 -0700 (PDT) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id n21sm9800333wmi.37.2018.04.05.05.39.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Thu, 05 Apr 2018 05:39:36 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Thu, 5 Apr 2018 13:39:20 +0100 Message-Id: <20180405123923.22671-5-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180405123923.22671-1-tvrtko.ursulin@linux.intel.com> References: <20180405123923.22671-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [PATCH 4/7] drm/i915/pmu: Add queued counter X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin We add a PMU counter to expose the number of requests which have been submitted from userspace but are not yet runnable due dependencies and unsignaled fences. This is useful to analyze the overall load of the system. v2: * Rebase for name change and re-order. * Drop floating point constant. (Chris Wilson) v3: * Change scale to 1024 for faster arithmetics. (Chris Wilson) Signed-off-by: Tvrtko Ursulin Reviewed-by: Chris Wilson --- drivers/gpu/drm/i915/i915_pmu.c | 40 +++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/intel_ringbuffer.h | 2 +- include/uapi/drm/i915_drm.h | 9 +++++++- 3 files changed, 45 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_pmu.c b/drivers/gpu/drm/i915/i915_pmu.c index eb60943671b3..07f5cac97b56 100644 --- a/drivers/gpu/drm/i915/i915_pmu.c +++ b/drivers/gpu/drm/i915/i915_pmu.c @@ -15,7 +15,8 @@ #define ENGINE_SAMPLE_MASK \ (BIT(I915_SAMPLE_BUSY) | \ BIT(I915_SAMPLE_WAIT) | \ - BIT(I915_SAMPLE_SEMA)) + BIT(I915_SAMPLE_SEMA) | \ + BIT(I915_SAMPLE_QUEUED)) #define ENGINE_SAMPLE_BITS (1 << I915_PMU_SAMPLE_BITS) @@ -199,6 +200,11 @@ static void engines_sample(struct drm_i915_private *dev_priv) update_sample(&engine->pmu.sample[I915_SAMPLE_SEMA], PERIOD, !!(val & RING_WAIT_SEMAPHORE)); + + if (engine->pmu.enable & BIT(I915_SAMPLE_QUEUED)) + update_sample(&engine->pmu.sample[I915_SAMPLE_QUEUED], + I915_SAMPLE_QUEUED_DIVISOR, + atomic_read(&engine->request_stats.queued)); } if (fw) @@ -296,6 +302,7 @@ engine_event_status(struct intel_engine_cs *engine, switch (sample) { case I915_SAMPLE_BUSY: case I915_SAMPLE_WAIT: + case I915_SAMPLE_QUEUED: break; case I915_SAMPLE_SEMA: if (INTEL_GEN(engine->i915) < 6) @@ -497,6 +504,9 @@ static u64 __i915_pmu_event_read(struct perf_event *event) } else { val = engine->pmu.sample[sample].cur; } + + if (sample == I915_SAMPLE_QUEUED) + val = div_u64(val, FREQUENCY); } else { switch (event->attr.config) { case I915_PMU_ACTUAL_FREQUENCY: @@ -752,6 +762,16 @@ static const struct attribute_group *i915_pmu_attr_groups[] = { { \ .sample = (__sample), \ .name = (__name), \ + .suffix = "unit", \ + .value = "ns", \ +} + +#define __engine_event_scale(__sample, __name, __scale) \ +{ \ + .sample = (__sample), \ + .name = (__name), \ + .suffix = "scale", \ + .value = (__scale), \ } static struct i915_ext_attribute * @@ -779,6 +799,9 @@ add_pmu_attr(struct perf_pmu_events_attr *attr, const char *name, return ++attr; } +/* No brackets or quotes below please. */ +#define I915_SAMPLE_QUEUED_SCALE 0.0009765625 + static struct attribute ** create_event_attributes(struct drm_i915_private *i915) { @@ -795,10 +818,14 @@ create_event_attributes(struct drm_i915_private *i915) static const struct { enum drm_i915_pmu_engine_sample sample; char *name; + char *suffix; + char *value; } engine_events[] = { __engine_event(I915_SAMPLE_BUSY, "busy"), __engine_event(I915_SAMPLE_SEMA, "sema"), __engine_event(I915_SAMPLE_WAIT, "wait"), + __engine_event_scale(I915_SAMPLE_QUEUED, "queued", + __stringify(I915_SAMPLE_QUEUED_SCALE)), }; unsigned int count = 0; struct perf_pmu_events_attr *pmu_attr = NULL, *pmu_iter; @@ -808,6 +835,9 @@ create_event_attributes(struct drm_i915_private *i915) enum intel_engine_id id; unsigned int i; + BUILD_BUG_ON(I915_SAMPLE_QUEUED_DIVISOR != + (1 / I915_SAMPLE_QUEUED_SCALE)); + /* Count how many counters we will be exposing. */ for (i = 0; i < ARRAY_SIZE(events); i++) { if (!config_status(i915, events[i].config)) @@ -885,13 +915,15 @@ create_event_attributes(struct drm_i915_private *i915) engine->instance, engine_events[i].sample)); - str = kasprintf(GFP_KERNEL, "%s-%s.unit", - engine->name, engine_events[i].name); + str = kasprintf(GFP_KERNEL, "%s-%s.%s", + engine->name, engine_events[i].name, + engine_events[i].suffix); if (!str) goto err; *attr_iter++ = &pmu_iter->attr.attr; - pmu_iter = add_pmu_attr(pmu_iter, str, "ns"); + pmu_iter = add_pmu_attr(pmu_iter, str, + engine_events[i].value); } } diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 616066f536c9..2324150fae06 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -414,7 +414,7 @@ struct intel_engine_cs { * * Our internal timer stores the current counters in this field. */ -#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_SEMA + 1) +#define I915_ENGINE_SAMPLE_MAX (I915_SAMPLE_QUEUED + 1) struct i915_pmu_sample sample[I915_ENGINE_SAMPLE_MAX]; } pmu; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7f5634ce8e88..6094cc9ca6d9 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -110,9 +110,13 @@ enum drm_i915_gem_engine_class { enum drm_i915_pmu_engine_sample { I915_SAMPLE_BUSY = 0, I915_SAMPLE_WAIT = 1, - I915_SAMPLE_SEMA = 2 + I915_SAMPLE_SEMA = 2, + I915_SAMPLE_QUEUED = 3 }; + /* Divide counter value by divisor to get the real value. */ +#define I915_SAMPLE_QUEUED_DIVISOR (1024) + #define I915_PMU_SAMPLE_BITS (4) #define I915_PMU_SAMPLE_MASK (0xf) #define I915_PMU_SAMPLE_INSTANCE_BITS (8) @@ -133,6 +137,9 @@ enum drm_i915_pmu_engine_sample { #define I915_PMU_ENGINE_SEMA(class, instance) \ __I915_PMU_ENGINE(class, instance, I915_SAMPLE_SEMA) +#define I915_PMU_ENGINE_QUEUED(class, instance) \ + __I915_PMU_ENGINE(class, instance, I915_SAMPLE_QUEUED) + #define __I915_PMU_OTHER(x) (__I915_PMU_ENGINE(0xff, 0xff, 0xf) + 1 + (x)) #define I915_PMU_ACTUAL_FREQUENCY __I915_PMU_OTHER(0)