From patchwork Fri Apr 6 20:53:49 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10327571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9AAA06038F for ; Fri, 6 Apr 2018 20:53:32 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 8AF49295FA for ; Fri, 6 Apr 2018 20:53:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 7F9EF2962A; Fri, 6 Apr 2018 20:53:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 247AA295FA for ; Fri, 6 Apr 2018 20:53:32 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B88FC6EACB; Fri, 6 Apr 2018 20:53:29 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2CE386EAB7 for ; Fri, 6 Apr 2018 20:53:28 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga103.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 06 Apr 2018 13:53:27 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,416,1517904000"; d="scan'208";a="31645954" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by orsmga008.jf.intel.com with ESMTP; 06 Apr 2018 13:53:27 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Fri, 6 Apr 2018 13:53:49 -0700 Message-Id: <20180406205349.8949-2-jose.souza@intel.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180406205349.8949-1-jose.souza@intel.com> References: <20180406205349.8949-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH 2/2] drm/i915/fbc: Resize CFB in non-full modeset paths X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paulo Zanoni Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP A simple page flip can cause the CFB required size to increase and if it is bigger than the currently allocated CFB it needs to be resized to activate FBC again. Until now this case was not being handled but CI is starting to get some of this errors. So here it will free the old CFB and a try to allocate the required CFB in the schedule activation work, it will happen after one vblank so is guarantee that FBC was completed disabled and is not using CFB. Also in case that there is no enough stolen memory to allocate the new CFB it will try 3 times per full modeset as the CFB requirement could be reduced in the next non-full modeset. Cc: Paulo Zanoni Signed-off-by: José Roberto de Souza Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105683 --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/intel_fbc.c | 46 +++++++++++++++++++++----------- 2 files changed, 33 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 5373b171bb96..4ce19b45f67d 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -566,6 +566,9 @@ struct intel_fbc { } work; const char *no_fbc_reason; + + bool cfb_try_resize; + u8 cfb_resize_tries_left; }; /* diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c index 573b034a02fd..7d77936db3ec 100644 --- a/drivers/gpu/drm/i915/intel_fbc.c +++ b/drivers/gpu/drm/i915/intel_fbc.c @@ -41,6 +41,9 @@ #include "intel_drv.h" #include "i915_drv.h" +static void __intel_fbc_cleanup_cfb(struct drm_i915_private *dev_priv); +static int intel_fbc_alloc_cfb(struct intel_crtc *crtc); + static inline bool fbc_supported(struct drm_i915_private *dev_priv) { return HAS_FBC(dev_priv); @@ -446,6 +449,15 @@ static void intel_fbc_work_fn(struct work_struct *__work) goto retry; } + if (fbc->cfb_try_resize && fbc->cfb_resize_tries_left) { + __intel_fbc_cleanup_cfb(dev_priv); + if (intel_fbc_alloc_cfb(crtc)) { + fbc->no_fbc_reason = "not enough stolen memory"; + fbc->cfb_resize_tries_left--; + goto out; + } + } + intel_fbc_hw_activate(dev_priv); work->scheduled = false; @@ -850,22 +862,6 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return false; } - /* It is possible for the required CFB size change without a - * crtc->disable + crtc->enable since it is possible to change the - * stride without triggering a full modeset. Since we try to - * over-allocate the CFB, there's a chance we may keep FBC enabled even - * if this happens, but if we exceed the current CFB size we'll have to - * disable FBC. Notice that it would be possible to disable FBC, wait - * for a frame, free the stolen node, then try to reenable FBC in case - * we didn't get any invalidate/deactivate calls, but this would require - * a lot of tracking just for a specific case. If we conclude it's an - * important case, we can implement it later. */ - if (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > - fbc->compressed_fb.size * fbc->threshold) { - fbc->no_fbc_reason = "CFB requirements changed"; - return false; - } - /* * Work around a problem on GEN9+ HW, where enabling FBC on a plane * having a Y offset that isn't divisible by 4 causes FIFO underrun @@ -877,6 +873,23 @@ static bool intel_fbc_can_activate(struct intel_crtc *crtc) return false; } + /* It is possible for the required CFB size change without a + * crtc->disable + crtc->enable since it is possible to change the + * stride without triggering a full modeset. Since we try to + * over-allocate the CFB, there's a chance we may keep FBC enabled even + * if this happens, but if we exceed the current CFB size we'll have to + * resize CFB. + */ + if (!drm_mm_node_allocated(&fbc->compressed_fb) || + (intel_fbc_calculate_cfb_size(dev_priv, &fbc->state_cache) > + fbc->compressed_fb.size * fbc->threshold)) { + fbc->cfb_try_resize = true; + DRM_DEBUG_KMS("CFB requirements have changed, activation \ + work will try to resize it"); + } else { + fbc->cfb_try_resize = false; + } + return true; } @@ -1208,6 +1221,7 @@ void intel_fbc_enable(struct intel_crtc *crtc, fbc->enabled = true; fbc->crtc = crtc; + fbc->cfb_resize_tries_left = 3; out: mutex_unlock(&fbc->lock); }