From patchwork Wed Apr 11 09:46:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tvrtko Ursulin X-Patchwork-Id: 10335241 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E5D986053C for ; Wed, 11 Apr 2018 09:46:50 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D291C28620 for ; Wed, 11 Apr 2018 09:46:50 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C6F852883C; Wed, 11 Apr 2018 09:46:50 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 45FAC28620 for ; Wed, 11 Apr 2018 09:46:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F10386E58B; Wed, 11 Apr 2018 09:46:47 +0000 (UTC) X-Original-To: Intel-gfx@lists.freedesktop.org Delivered-To: Intel-gfx@lists.freedesktop.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 702726E595 for ; Wed, 11 Apr 2018 09:46:46 +0000 (UTC) Received: by mail-wr0-x244.google.com with SMTP id u11so1104587wri.12 for ; Wed, 11 Apr 2018 02:46:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ursulin-net.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=nuuihA8bKRBPsDDOkxwDlVV2X9fBC4RWXpt1GawOY3o=; b=c8enahRMlBqcS+ydmJd7Llmi6WaZxcNh+5xNpKa8vIay0hrKWqH4BZhd9N6XOXIbdF XJF3WCeYbxPz9YhJnVmB3d6ZSOLD/7rC45zCSpC3om2n4l15WD2p5iQdGYu44xzCQaXp 8MUzbQpJBsw1ybJVLRY7ds/mDBD24u/LIUfnas/yQq6cRYdfmxNfSCG8QPinjMxpEgYy yv0tNVCw9fTVWnmkpKpyz6xvgUY3WidxpGhqeL4ciVNQVgPuGm7MC10X+4qXSnRhyi1A jB3g2RpBolJpvXwrFu2VIUN4+7Zn+aacrhXU+4b+XZ3uL1Beq0oPEyMuNHgX016bR5c3 T7bQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=nuuihA8bKRBPsDDOkxwDlVV2X9fBC4RWXpt1GawOY3o=; b=nxNQJXSHZ4Pp6pV9hHv+zKP9HroCh8M2bLn+JQzypWhWPh44jFEoH5pmPkQva4izOi 7VIk2O1fasr19YT6StjpMboFnz6Kymt+WY09in62bc0M7Hf/NuYp78IpqExRKNi0jlgi 8pPjCHgpnPvFRCBXL8m//6L7vr2ENYTPT8eXMsUL8ZPA6cFaSq+4MLCTbKxu0Zc5EoB9 mLWN0sx3HCb2F0ldwWgu2Opoj2dgXqx+SxoJ0qUPUPo8mgmc7oACiYKOLGtM1zp0J2p4 uJ39ivA+7+IhRBjIDHxLHEFnbeqmw65DgiTqM/iaBwK+egiSWlRhuB6+9iB/mvLH1JH+ GpBg== X-Gm-Message-State: ALQs6tDfRu54iCZWicenEtD8LJuZNZiPRjTYjia1I2wa/+02KBCEF3pn NOdSUz4udc7uI8rI+6D4QcKFpjEW X-Google-Smtp-Source: AIpwx49oeFONRS/Jc3riku6VTX9o8jUXCJzJZDtPrvJeWR6bJXbHiRfbFlTEDOpmDUYJl8eKsz1wew== X-Received: by 10.223.136.217 with SMTP id g25mr3012902wrg.203.1523440004581; Wed, 11 Apr 2018 02:46:44 -0700 (PDT) Received: from localhost.localdomain ([95.146.144.186]) by smtp.gmail.com with ESMTPSA id f7sm1067088wrf.95.2018.04.11.02.46.39 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Wed, 11 Apr 2018 02:46:39 -0700 (PDT) From: Tvrtko Ursulin X-Google-Original-From: Tvrtko Ursulin To: Intel-gfx@lists.freedesktop.org Date: Wed, 11 Apr 2018 10:46:31 +0100 Message-Id: <20180411094631.14959-1-tvrtko.ursulin@linux.intel.com> X-Mailer: git-send-email 2.14.1 In-Reply-To: <20180314140539.9287-1-tvrtko.ursulin@linux.intel.com> References: <20180314140539.9287-1-tvrtko.ursulin@linux.intel.com> Subject: [Intel-gfx] [RFC v2] drm/i915: Engine discovery query X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP From: Tvrtko Ursulin Engine discovery query allows userspace to enumerate engines, probe their configuration features, all without needing to maintain the internal PCI ID based database. A new query for the generic i915 query ioctl is added named DRM_I915_QUERY_ENGINE_INFO, together with accompanying structure drm_i915_query_engine_info. The address of latter should be passed to the kernel in the query.data_ptr field, and should be large enough for the kernel to fill out all known engines as struct drm_i915_engine_info elements trailing the query. As with other queries, setting the item query length to zero allows userspace to query minimum required buffer size. Enumerated engines have common type mask which can be used to query all hardware engines, versus engines userspace can submit to using the execbuf uAPI. Engines also have capabilities which are per engine class namespace of bits describing features not present on all engine instances. v2: * Fixed HEVC assignment. * Reorder some fields, rename type to flags, increase width. (Lionel) * No need to allocate temporary storage if we do it engine by engine. (Lionel) Signed-off-by: Tvrtko Ursulin Cc: Chris Wilson Cc: Jon Bloomfield Cc: Dmitry Rogozhkin Cc: Lionel Landwerlin Cc: Joonas Lahtinen Reviewed-by: Lionel Landwerlin --- This is RFC for now since it is not very usable before the new execbuf API or virtual engine queue submission gets closer. In this version I have added capability of distinguishing between hardware engines and ABI engines. This is to account for probable future use cases like virtualization, where guest might only see one engine instance, but will want to know overall hardware capabilities in order to tune its behaviour. In general I think we will have to wait a bit before defining the final look of the uAPI, but in the meantime I thought it useful to share as RFC. --- drivers/gpu/drm/i915/i915_query.c | 63 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/intel_engine_cs.c | 2 ++ drivers/gpu/drm/i915/intel_ringbuffer.h | 3 ++ include/uapi/drm/i915_drm.h | 46 ++++++++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_query.c b/drivers/gpu/drm/i915/i915_query.c index 3ace929dd90f..a1c0e3acc882 100644 --- a/drivers/gpu/drm/i915/i915_query.c +++ b/drivers/gpu/drm/i915/i915_query.c @@ -82,9 +82,72 @@ static int query_topology_info(struct drm_i915_private *dev_priv, return total_length; } +static int +query_engine_info(struct drm_i915_private *i915, + struct drm_i915_query_item *query_item) +{ + struct drm_i915_query_engine_info __user *query_ptr = + u64_to_user_ptr(query_item->data_ptr); + struct drm_i915_engine_info __user *info_ptr = &query_ptr->engines[0]; + struct drm_i915_query_engine_info query; + struct intel_engine_cs *engine; + enum intel_engine_id id; + int len; + + if (query_item->flags) + return -EINVAL; + + len = sizeof(struct drm_i915_query_engine_info) + + I915_NUM_ENGINES * sizeof(struct drm_i915_engine_info); + + if (!query_item->length) + return len; + else if (query_item->length < len) + return -EINVAL; + + if (copy_from_user(&query, query_ptr, sizeof(query))) + return -EFAULT; + + if (query.num_engines || query.rsvd[0] || query.rsvd[1] || + query.rsvd[2]) + return -EINVAL; + + if (!access_ok(VERIFY_WRITE, query_ptr, query_item->length)) + return -EFAULT; + + for_each_engine(engine, i915, id) { + struct drm_i915_engine_info info; + + if (__copy_from_user(&info, info_ptr, sizeof(info))) + return -EFAULT; + + if (info.flags || info.class || info.instance || + info.capabilities || info.rsvd0 || info.rsvd1[0] || + info.rsvd1[1]) + return -EINVAL; + + info.class = engine->uabi_class; + info.instance = engine->instance; + info.flags = I915_ENGINE_FLAG_PHYSICAL | I915_ENGINE_FLAG_ABI; + info.capabilities = engine->capabilities; + + if (__copy_to_user(info_ptr, &info, sizeof(info))) + return -EFAULT; + + query.num_engines++; + info_ptr++; + } + + if (__copy_to_user(query_ptr, &query, sizeof(query))) + return -EFAULT; + + return len; +} + static int (* const i915_query_funcs[])(struct drm_i915_private *dev_priv, struct drm_i915_query_item *query_item) = { query_topology_info, + query_engine_info, }; int i915_query_ioctl(struct drm_device *dev, void *data, struct drm_file *file) diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c index 12486d8f534b..9d26c34dfec4 100644 --- a/drivers/gpu/drm/i915/intel_engine_cs.c +++ b/drivers/gpu/drm/i915/intel_engine_cs.c @@ -294,6 +294,8 @@ intel_engine_setup(struct drm_i915_private *dev_priv, engine->mmio_base = __engine_mmio_base(dev_priv, info->mmio_bases); engine->class = info->class; engine->instance = info->instance; + if (INTEL_GEN(dev_priv) >= 8 && info->instance == 0) + engine->capabilities = I915_VCS_CLASS_CAPABILITY_HEVC; engine->uabi_id = info->uabi_id; engine->uabi_class = intel_engine_classes[info->class].uabi_class; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 256d58487559..b23be52fc882 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -330,6 +330,9 @@ struct intel_engine_cs { u8 class; u8 instance; + + u32 capabilities; + u32 context_size; u32 mmio_base; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 7f5634ce8e88..2eafb677cd40 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1620,6 +1620,7 @@ struct drm_i915_perf_oa_config { struct drm_i915_query_item { __u64 query_id; #define DRM_I915_QUERY_TOPOLOGY_INFO 1 +#define DRM_I915_QUERY_ENGINE_INFO 2 /* * When set to zero by userspace, this is filled with the size of the @@ -1717,6 +1718,51 @@ struct drm_i915_query_topology_info { __u8 data[]; }; +/** + * struct drm_i915_engine_info + * + * Describes one engine known to the driver, whether or not is physical engine + * only, or it can also be targetted from userspace, and what are its + * capabilities where applicable. + */ +struct drm_i915_engine_info { + /** Engine flags. */ + __u64 flags; +#define I915_ENGINE_FLAG_PHYSICAL (1 << 0) +#define I915_ENGINE_FLAG_ABI (1 << 1) + + /** Engine class as in enum drm_i915_gem_engine_class. */ + __u16 class; + + /** Engine instance number. */ + __u16 instance; + + __u32 rsvd0; + + /** Capabilities of this engine. */ + __u64 capabilities; +#define I915_VCS_CLASS_CAPABILITY_HEVC (1 << 0) + + __u64 rsvd1[2]; +}; + +/** + * struct drm_i915_query_engine_info + * + * Engine info query enumerates all the engines known to the driver returning + * the array of struct drm_i915_engine_info structures. + */ +struct drm_i915_query_engine_info { + /** Number of struct drm_i915_engine_info structs following. */ + __u32 num_engines; + + /** MBZ */ + __u32 rsvd[3]; + + /** Marker for drm_i915_engine_info structures. */ + struct drm_i915_engine_info engines[]; +}; + #if defined(__cplusplus) } #endif