From patchwork Thu Apr 12 13:52:37 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mika Kuoppala X-Patchwork-Id: 10338571 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0C987602D8 for ; Thu, 12 Apr 2018 13:53:13 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 04E5F288AC for ; Thu, 12 Apr 2018 13:53:13 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id ED3C3288C3; Thu, 12 Apr 2018 13:53:12 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A92E3288AC for ; Thu, 12 Apr 2018 13:53:11 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id BABC76E48E; Thu, 12 Apr 2018 13:53:10 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga07.intel.com (mga07.intel.com [134.134.136.100]) by gabe.freedesktop.org (Postfix) with ESMTPS id 8747C6E48E for ; Thu, 12 Apr 2018 13:53:09 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga003.jf.intel.com ([10.7.209.27]) by orsmga105.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 12 Apr 2018 06:53:08 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,441,1517904000"; d="scan'208";a="42800606" Received: from rosetta.fi.intel.com ([10.237.72.186]) by orsmga003.jf.intel.com with ESMTP; 12 Apr 2018 06:53:07 -0700 Received: by rosetta.fi.intel.com (Postfix, from userid 1000) id DF56E840059; Thu, 12 Apr 2018 16:52:38 +0300 (EEST) From: Mika Kuoppala To: intel-gfx@lists.freedesktop.org Date: Thu, 12 Apr 2018 16:52:37 +0300 Message-Id: <20180412135237.9393-1-mika.kuoppala@linux.intel.com> X-Mailer: git-send-email 2.14.1 Subject: [Intel-gfx] [PATCH] drm/i915: Enforce read order into the hardware status page csb X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rodrigo , Vivi@rosetta.fi.intel.com MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Read ordering on cpu can be out of order and speculative. In addition, the access to the hardware status page is snooped. This raises a concern that we might use the HWSP in an unexpected way as we may load the head of a cbs entry before we access the tail. Concerns like that the coherency protocol is tied somehow to the tail read snoop. To enforce that we really do read the tail before we fetch the csb entry pointed by head, insert a read memory barrier after we have read the tail. This fixes, or masks due to added latency, context status buffer incoherence on cnl, where we see an old context status entry still on that a csb slot. References: https://bugs.freedesktop.org/show_bug.cgi?id=105888 Cc: Chris Wilson Cc: Rafael Antognolli Cc: Vivi, Rodrigo Signed-off-by: Mika Kuoppala --- drivers/gpu/drm/i915/intel_lrc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index c7c85134a84a..5378391e1e71 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -969,6 +969,8 @@ static void execlists_submission_tasklet(unsigned long data) head = execlists->csb_head; tail = READ_ONCE(buf[write_idx]); + /* Enforce ordering of reads into the HWSP */ + rmb(); } GEM_TRACE("%s cs-irq head=%d [%d%s], tail=%d [%d%s]\n", engine->name,