From patchwork Wed Apr 18 22:43:11 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: "Souza, Jose" X-Patchwork-Id: 10348991 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3D4816053F for ; Wed, 18 Apr 2018 22:43:24 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2DC6328710 for ; Wed, 18 Apr 2018 22:43:24 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2298B288A2; Wed, 18 Apr 2018 22:43:24 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id CEC8328710 for ; Wed, 18 Apr 2018 22:43:23 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2A8696E59C; Wed, 18 Apr 2018 22:43:23 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTPS id 3B2116E1F7 for ; Wed, 18 Apr 2018 22:43:06 +0000 (UTC) X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from fmsmga005.fm.intel.com ([10.253.24.32]) by orsmga101.jf.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 18 Apr 2018 15:43:06 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.48,466,1517904000"; d="scan'208";a="221527341" Received: from josouza-mobl.jf.intel.com ([10.24.11.40]) by fmsmga005.fm.intel.com with ESMTP; 18 Apr 2018 15:43:05 -0700 From: =?UTF-8?q?Jos=C3=A9=20Roberto=20de=20Souza?= To: intel-gfx@lists.freedesktop.org Date: Wed, 18 Apr 2018 15:43:11 -0700 Message-Id: <20180418224311.16577-9-jose.souza@intel.com> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180418224311.16577-1-jose.souza@intel.com> References: <20180418224311.16577-1-jose.souza@intel.com> MIME-Version: 1.0 Subject: [Intel-gfx] [PATCH v2 9/9] drm/i915/dp: Avoid concurrent access when HW is using aux ch X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dhinakaran Pandiyan Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP This will avoid some cases of concurrent access to aux ch registers when hardware is using it(HW uses it when PSR, GTC and aux frame is enabled). It is just first step to see if this scenario happens, if so it will be properly handled as described in bspec. Signed-off-by: José Roberto de Souza Cc: Dhinakaran Pandiyan --- New patch in this series, this is replacing to the patches in this series that was exiting PSR before a aux transaction. As discussed with Dhinakaran, let's check first if this scenary happens if so I will bring those patches back. drivers/gpu/drm/i915/intel_dp.c | 18 +++++++++++++++--- 1 file changed, 15 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c index 258e23961456..74abd4cd93dd 100644 --- a/drivers/gpu/drm/i915/intel_dp.c +++ b/drivers/gpu/drm/i915/intel_dp.c @@ -1062,7 +1062,7 @@ static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp, DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); } -static bool intel_dp_aux_is_busy(struct intel_dp *intel_dp) +static bool intel_dp_aux_is_busy(struct intel_dp *intel_dp, unsigned int tries) { struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = @@ -1073,7 +1073,7 @@ static bool intel_dp_aux_is_busy(struct intel_dp *intel_dp) ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); - for (try = 3; try; try--) { + for (try = tries; try; try--) { status = I915_READ_NOTRACE(ch_ctl); if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) return false; @@ -1127,7 +1127,7 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, intel_dp_check_edp(intel_dp); /* Try to wait for any previous AUX channel activity */ - if (intel_dp_aux_is_busy(intel_dp)) { + if (intel_dp_aux_is_busy(intel_dp, 3)) { ret = -EBUSY; goto out; } @@ -1148,6 +1148,18 @@ intel_dp_aux_xfer(struct intel_dp *intel_dp, /* Must try at least 3 times according to DP spec */ for (try = 0; try < 5; try++) { + /* WA: try to avoid concurrent access to aux ch + * registers while hardware is using it, the other + * way is not handled at all. + */ + if (intel_dp_aux_is_busy(intel_dp, 1)) { + DRM_ERROR("Aux ch %c is busy, hw is using it", + aux_ch_name(intel_dp->aux_ch)); + /* sleep for a transaction time */ + usleep_range(400, 500); + continue; + } + /* Load the send data into the aux channel data registers */ for (i = 0; i < send_bytes; i += 4) I915_WRITE(ch_data[i >> 2],