diff mbox

[v3,3/4] drm/i915/debugfs: Print sink PSR status

Message ID 20180420222758.6168-3-jose.souza@intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Souza, Jose April 20, 2018, 10:27 p.m. UTC 
IGT tests could be improved with sink status, knowing for sure that
hardware have activate or exit PSR.

Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---

No changes since v2, Dhinakaran asked to not merge this patch in v2
because reading i915_edp_psr_status was causing PSR to exit but now
with 'drm/i915/psr: Prevent PSR exit when a non-pipe related register
is written' it is fixed.

 drivers/gpu/drm/i915/i915_debugfs.c | 29 +++++++++++++++++++++++++++++
 1 file changed, 29 insertions(+)

Comments

Dhinakaran Pandiyan April 25, 2018, 12:18 a.m. UTC | #1 
On Fri, 2018-04-20 at 15:27 -0700, José Roberto de Souza wrote:
> IGT tests could be improved with sink status, knowing for sure that
> hardware have activate or exit PSR.
> 
> Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> 
> No changes since v2, Dhinakaran asked to not merge this patch in v2
> because reading i915_edp_psr_status was causing PSR to exit but now
> with 'drm/i915/psr: Prevent PSR exit when a non-pipe related register
> is written' it is fixed.
> 

Do you mind adding "reading i915_edp_psr_status was causing PSR to exit
but now with 'drm/i915/psr: Prevent PSR exit when a non-pipe related
register is written' it is fixed." to the commit message?



>  drivers/gpu/drm/i915/i915_debugfs.c | 29 +++++++++++++++++++++++++++++
>  1 file changed, 29 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 2f05f5262bba..536d93322451 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)
>  	return "unknown";
>  }
>  
> +static const char *psr_sink_status(u8 val)
> +{
> +	static const char * const sink_status[] = {
> +		"inactive",
> +		"transition to active, capture and display",
> +		"active, display from RFB",
> +		"active, capture and display on sink device timings",
> +		"transition to inactive, capture and display, timing re-sync",
> +		"reserved",
> +		"reserved",
> +		"sink internal error"
> +	};
> +
> +	val &= DP_PSR_SINK_STATE_MASK;
> +	if (val < ARRAY_SIZE(sink_status))
> +		return sink_status[val];
> +
> +	return "unknown";
> +}
> +
>  static int i915_edp_psr_status(struct seq_file *m, void *data)
>  {
>  	struct drm_i915_private *dev_priv = node_to_i915(m->private);
> @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
>  		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
>  			   psr2, psr2_live_status(psr2));
>  	}
> +
> +	if (dev_priv->psr.enabled) {
> +		struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;
> +		u8 val;
> +
> +		if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) == 1)
> +			seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
> +				   psr_sink_status(val));
> +	}
>  	mutex_unlock(&dev_priv->psr.lock);
>  
>  	if (READ_ONCE(dev_priv->psr.debug)) {
Souza, Jose April 25, 2018, 8:33 p.m. UTC | #2 
On Tue, 2018-04-24 at 17:18 -0700, Dhinakaran Pandiyan wrote:
> 

> 

> On Fri, 2018-04-20 at 15:27 -0700, José Roberto de Souza wrote:

> > IGT tests could be improved with sink status, knowing for sure that

> > hardware have activate or exit PSR.

> > 

> > Reviewed-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>

> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>

> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>

> > ---

> > 

> > No changes since v2, Dhinakaran asked to not merge this patch in v2

> > because reading i915_edp_psr_status was causing PSR to exit but now

> > with 'drm/i915/psr: Prevent PSR exit when a non-pipe related

> > register

> > is written' it is fixed.

> > 

> 

> Do you mind adding "reading i915_edp_psr_status was causing PSR to

> exit

> but now with 'drm/i915/psr: Prevent PSR exit when a non-pipe related

> register is written' it is fixed." to the commit message?


Done

> 

> 

> 

> >  drivers/gpu/drm/i915/i915_debugfs.c | 29

> > +++++++++++++++++++++++++++++

> >  1 file changed, 29 insertions(+)

> > 

> > diff --git a/drivers/gpu/drm/i915/i915_debugfs.c

> > b/drivers/gpu/drm/i915/i915_debugfs.c

> > index 2f05f5262bba..536d93322451 100644

> > --- a/drivers/gpu/drm/i915/i915_debugfs.c

> > +++ b/drivers/gpu/drm/i915/i915_debugfs.c

> > @@ -2603,6 +2603,26 @@ static const char *psr2_live_status(u32 val)

> >  	return "unknown";

> >  }

> >  

> > +static const char *psr_sink_status(u8 val)

> > +{

> > +	static const char * const sink_status[] = {

> > +		"inactive",

> > +		"transition to active, capture and display",

> > +		"active, display from RFB",

> > +		"active, capture and display on sink device

> > timings",

> > +		"transition to inactive, capture and display,

> > timing re-sync",

> > +		"reserved",

> > +		"reserved",

> > +		"sink internal error"

> > +	};

> > +

> > +	val &= DP_PSR_SINK_STATE_MASK;

> > +	if (val < ARRAY_SIZE(sink_status))

> > +		return sink_status[val];

> > +

> > +	return "unknown";

> > +}

> > +

> >  static int i915_edp_psr_status(struct seq_file *m, void *data)

> >  {

> >  	struct drm_i915_private *dev_priv = node_to_i915(m-

> > >private);

> > @@ -2684,6 +2704,15 @@ static int i915_edp_psr_status(struct

> > seq_file *m, void *data)

> >  		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",

> >  			   psr2, psr2_live_status(psr2));

> >  	}

> > +

> > +	if (dev_priv->psr.enabled) {

> > +		struct drm_dp_aux *aux = &dev_priv->psr.enabled-

> > >aux;

> > +		u8 val;

> > +

> > +		if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) ==

> > 1)

> > +			seq_printf(m, "Sink PSR status: 0x%x

> > [%s]\n", val,

> > +				   psr_sink_status(val));

> > +	}

> >  	mutex_unlock(&dev_priv->psr.lock);

> >  

> >  	if (READ_ONCE(dev_priv->psr.debug)) {

> 

>
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 2f05f5262bba..536d93322451 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2603,6 +2603,26 @@  static const char *psr2_live_status(u32 val)
 	return "unknown";
 }
 
+static const char *psr_sink_status(u8 val)
+{
+	static const char * const sink_status[] = {
+		"inactive",
+		"transition to active, capture and display",
+		"active, display from RFB",
+		"active, capture and display on sink device timings",
+		"transition to inactive, capture and display, timing re-sync",
+		"reserved",
+		"reserved",
+		"sink internal error"
+	};
+
+	val &= DP_PSR_SINK_STATE_MASK;
+	if (val < ARRAY_SIZE(sink_status))
+		return sink_status[val];
+
+	return "unknown";
+}
+
 static int i915_edp_psr_status(struct seq_file *m, void *data)
 {
 	struct drm_i915_private *dev_priv = node_to_i915(m->private);
@@ -2684,6 +2704,15 @@  static int i915_edp_psr_status(struct seq_file *m, void *data)
 		seq_printf(m, "EDP_PSR2_STATUS: %x [%s]\n",
 			   psr2, psr2_live_status(psr2));
 	}
+
+	if (dev_priv->psr.enabled) {
+		struct drm_dp_aux *aux = &dev_priv->psr.enabled->aux;
+		u8 val;
+
+		if (drm_dp_dpcd_readb(aux, DP_PSR_STATUS, &val) == 1)
+			seq_printf(m, "Sink PSR status: 0x%x [%s]\n", val,
+				   psr_sink_status(val));
+	}
 	mutex_unlock(&dev_priv->psr.lock);
 
 	if (READ_ONCE(dev_priv->psr.debug)) {