From patchwork Thu May 3 06:37:29 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10377201 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5770F603B4 for ; Thu, 3 May 2018 06:40:01 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 48694251F9 for ; Thu, 3 May 2018 06:40:01 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3C81D28E2B; Thu, 3 May 2018 06:40:01 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 9B92F251F9 for ; Thu, 3 May 2018 06:40:00 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2D8E56E6E6; Thu, 3 May 2018 06:39:45 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 051F76E6E8 for ; Thu, 3 May 2018 06:39:42 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11578295-1500050 for multiple; Thu, 03 May 2018 07:39:37 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Thu, 03 May 2018 07:39:35 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 3 May 2018 07:37:29 +0100 Message-Id: <20180503063757.22238-43-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503063757.22238-1-chris@chris-wilson.co.uk> References: <20180503063757.22238-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 43/71] drm/i915: Track HAS_RPS alongside HAS_RC6 in the device info X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP For consistency (and elegance!), add intel_device_info.has_rps. The immediate boon is that RPS support is now emitted along the other capabilities in the debug log and after errors. Signed-off-by: Chris Wilson Reviewed-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_pci.c | 6 ++++++ drivers/gpu/drm/i915/intel_device_info.h | 1 + drivers/gpu/drm/i915/intel_gt_pm.c | 20 ++++++++++++++++---- 4 files changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 996769c9617a..21f56684028f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2503,6 +2503,8 @@ intel_info(const struct drm_i915_private *dev_priv) #define HAS_RC6p(dev_priv) ((dev_priv)->info.has_rc6p) #define HAS_RC6pp(dev_priv) (false) /* HW was never validated */ +#define HAS_RPS(dev_priv) (INTEL_INFO(dev_priv)->has_rps) + #define HAS_CSR(dev_priv) ((dev_priv)->info.has_csr) #define HAS_RUNTIME_PM(dev_priv) ((dev_priv)->info.has_runtime_pm) diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c index 4364922e935d..b0070e914228 100644 --- a/drivers/gpu/drm/i915/i915_pci.c +++ b/drivers/gpu/drm/i915/i915_pci.c @@ -235,6 +235,7 @@ static const struct intel_device_info intel_ironlake_m_info = { GEN5_FEATURES, PLATFORM(INTEL_IRONLAKE), .is_mobile = 1, .has_fbc = 1, + .has_rps = true, }; #define GEN6_FEATURES \ @@ -246,6 +247,7 @@ static const struct intel_device_info intel_ironlake_m_info = { .has_llc = 1, \ .has_rc6 = 1, \ .has_rc6p = 1, \ + .has_rps = true, \ .has_aliasing_ppgtt = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ GEN_DEFAULT_PAGE_SIZES, \ @@ -290,6 +292,7 @@ static const struct intel_device_info intel_sandybridge_m_gt2_info = { .has_llc = 1, \ .has_rc6 = 1, \ .has_rc6p = 1, \ + .has_rps = true, \ .has_aliasing_ppgtt = 1, \ .has_full_ppgtt = 1, \ GEN_DEFAULT_PIPEOFFSETS, \ @@ -343,6 +346,7 @@ static const struct intel_device_info intel_valleyview_info = { .has_psr = 1, .has_runtime_pm = 1, .has_rc6 = 1, + .has_rps = true, .has_gmch_display = 1, .has_hotplug = 1, .has_aliasing_ppgtt = 1, @@ -437,6 +441,7 @@ static const struct intel_device_info intel_cherryview_info = { .has_runtime_pm = 1, .has_resource_streamer = 1, .has_rc6 = 1, + .has_rps = true, .has_logical_ring_contexts = 1, .has_gmch_display = 1, .has_aliasing_ppgtt = 1, @@ -510,6 +515,7 @@ static const struct intel_device_info intel_skylake_gt4_info = { .has_csr = 1, \ .has_resource_streamer = 1, \ .has_rc6 = 1, \ + .has_rps = true, \ .has_dp_mst = 1, \ .has_logical_ring_contexts = 1, \ .has_logical_ring_preemption = 1, \ diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h index 3f9881c548ef..2e01bc6eb5a2 100644 --- a/drivers/gpu/drm/i915/intel_device_info.h +++ b/drivers/gpu/drm/i915/intel_device_info.h @@ -103,6 +103,7 @@ enum intel_platform { func(has_psr); \ func(has_rc6); \ func(has_rc6p); \ + func(has_rps); \ func(has_resource_streamer); \ func(has_runtime_pm); \ func(has_snoop); \ diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c index 79cb4dbafbea..f096c5cb84ba 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/intel_gt_pm.c @@ -724,6 +724,9 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; + if (!HAS_RPS(dev_priv)) + return; + mutex_lock(&rps->lock); if (rps->enabled) { u8 freq; @@ -753,6 +756,9 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; + if (!HAS_RPS(dev_priv)) + return; + /* * Flush our bottom-half so that it does not race with us * setting the idle frequency and so that it is bounded by @@ -780,6 +786,9 @@ void gen6_rps_boost(struct i915_request *rq, struct intel_rps_client *client) unsigned long flags; bool boost; + if (!HAS_RPS(rq->i915)) + return; + /* * This is intentionally racy! We peek at the state here, then * validate inside the RPS worker. @@ -922,8 +931,10 @@ static bool sanitize_rc6(struct drm_i915_private *i915) struct intel_device_info *info = mkwrite_device_info(i915); /* Powersaving is controlled by the host when inside a VM */ - if (intel_vgpu_active(i915)) + if (intel_vgpu_active(i915)) { info->has_rc6 = 0; + info->has_rps = 0; + } if (info->has_rc6 && IS_GEN9_LP(i915) && !bxt_check_bios_rc6_setup(i915)) { @@ -2554,7 +2565,7 @@ static void intel_disable_rps(struct drm_i915_private *i915) valleyview_disable_rps(i915); else if (INTEL_GEN(i915) >= 6) gen6_disable_rps(i915); - else if (IS_IRONLAKE_M(i915)) + else if (INTEL_GEN(i915) >= 5) ironlake_disable_drps(i915); i915->gt_pm.rps.enabled = false; @@ -2624,7 +2635,7 @@ static void intel_enable_rps(struct drm_i915_private *i915) gen8_enable_rps(i915); } else if (INTEL_GEN(i915) >= 6) { gen6_enable_rps(i915); - } else if (IS_IRONLAKE_M(i915)) { + } else if (INTEL_GEN(i915) >= 5) { ironlake_enable_drps(i915); intel_init_emon(i915); } @@ -2648,7 +2659,8 @@ void intel_enable_gt_powersave(struct drm_i915_private *i915) if (HAS_RC6(i915)) intel_enable_rc6(i915); - intel_enable_rps(i915); + if (HAS_RPS(i915)) + intel_enable_rps(i915); if (HAS_LLC(i915)) intel_enable_llc_pstate(i915);