From patchwork Thu May 3 06:37:31 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10377209 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 799CA603B4 for ; Thu, 3 May 2018 06:40:14 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 61683290D0 for ; Thu, 3 May 2018 06:40:14 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4CAF428E74; Thu, 3 May 2018 06:40:14 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4E14A28E74 for ; Thu, 3 May 2018 06:40:12 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4869C6E6AB; Thu, 3 May 2018 06:39:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 12A516E69F for ; Thu, 3 May 2018 06:39:47 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11578299-1500050 for multiple; Thu, 03 May 2018 07:39:41 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Thu, 03 May 2018 07:39:40 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 3 May 2018 07:37:31 +0100 Message-Id: <20180503063757.22238-45-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503063757.22238-1-chris@chris-wilson.co.uk> References: <20180503063757.22238-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 45/71] drm/i915: Reorder GT interface code X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Try to order the intel_gt_pm code to match the order it is used: init enable disable cleanup Signed-off-by: Chris Wilson Reviewed-by: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_gt_pm.c | 170 ++++++++++++++--------------- drivers/gpu/drm/i915/intel_gt_pm.h | 5 +- 2 files changed, 88 insertions(+), 87 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c index f8b75814796d..b69ddb5be3e4 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/intel_gt_pm.c @@ -2400,6 +2400,18 @@ static void intel_init_emon(struct drm_i915_private *dev_priv) dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); } +void intel_sanitize_gt_powersave(struct drm_i915_private *i915) +{ + i915->gt_pm.rps.enabled = true; /* force RPS disabling */ + i915->gt_pm.rc6.enabled = true; /* force RC6 disabling */ + intel_disable_gt_powersave(i915); + + if (INTEL_GEN(i915) >= 11) + gen11_reset_rps_interrupts(i915); + else + gen6_reset_rps_interrupts(i915); +} + void intel_init_gt_powersave(struct drm_i915_private *i915) { struct intel_rps *rps = &i915->gt_pm.rps; @@ -2482,91 +2494,6 @@ void intel_init_gt_powersave(struct drm_i915_private *i915) mutex_unlock(&rps->lock); } -void intel_cleanup_gt_powersave(struct drm_i915_private *i915) -{ - if (IS_VALLEYVIEW(i915)) - valleyview_cleanup_gt_powersave(i915); - - if (!HAS_RC6(i915)) - intel_runtime_pm_put(i915); -} - -void intel_sanitize_gt_powersave(struct drm_i915_private *i915) -{ - i915->gt_pm.rps.enabled = true; /* force RPS disabling */ - i915->gt_pm.rc6.enabled = true; /* force RC6 disabling */ - intel_disable_gt_powersave(i915); - - if (INTEL_GEN(i915) >= 11) - gen11_reset_rps_interrupts(i915); - else - gen6_reset_rps_interrupts(i915); -} - -static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) -{ - lockdep_assert_held(&i915->gt_pm.rps.lock); - - if (!i915->gt_pm.llc_pstate.enabled) - return; - - /* Currently there is no HW configuration to be done to disable. */ - - i915->gt_pm.llc_pstate.enabled = false; -} - -static void intel_disable_rc6(struct drm_i915_private *i915) -{ - lockdep_assert_held(&i915->gt_pm.rps.lock); - - if (!i915->gt_pm.rc6.enabled) - return; - - if (INTEL_GEN(i915) >= 9) - gen9_disable_rc6(i915); - else if (IS_CHERRYVIEW(i915)) - cherryview_disable_rc6(i915); - else if (IS_VALLEYVIEW(i915)) - valleyview_disable_rc6(i915); - else if (INTEL_GEN(i915) >= 6) - gen6_disable_rc6(i915); - - i915->gt_pm.rc6.enabled = false; -} - -static void intel_disable_rps(struct drm_i915_private *i915) -{ - lockdep_assert_held(&i915->gt_pm.rps.lock); - - if (!i915->gt_pm.rps.enabled) - return; - - if (INTEL_GEN(i915) >= 9) - gen9_disable_rps(i915); - else if (IS_CHERRYVIEW(i915)) - cherryview_disable_rps(i915); - else if (IS_VALLEYVIEW(i915)) - valleyview_disable_rps(i915); - else if (INTEL_GEN(i915) >= 6) - gen6_disable_rps(i915); - else if (INTEL_GEN(i915) >= 5) - ironlake_disable_drps(i915); - - i915->gt_pm.rps.enabled = false; -} - -void intel_disable_gt_powersave(struct drm_i915_private *i915) -{ - mutex_lock(&i915->gt_pm.rps.lock); - - intel_disable_rc6(i915); - intel_disable_rps(i915); - if (HAS_LLC(i915)) - intel_disable_llc_pstate(i915); - - mutex_unlock(&i915->gt_pm.rps.lock); -} - static inline void intel_enable_llc_pstate(struct drm_i915_private *i915) { lockdep_assert_held(&i915->gt_pm.rps.lock); @@ -2651,6 +2578,79 @@ void intel_enable_gt_powersave(struct drm_i915_private *i915) mutex_unlock(&i915->gt_pm.rps.lock); } +static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) +{ + lockdep_assert_held(&i915->gt_pm.rps.lock); + + if (!i915->gt_pm.llc_pstate.enabled) + return; + + /* Currently there is no HW configuration to be done to disable. */ + + i915->gt_pm.llc_pstate.enabled = false; +} + +static void intel_disable_rc6(struct drm_i915_private *i915) +{ + lockdep_assert_held(&i915->gt_pm.rps.lock); + + if (!i915->gt_pm.rc6.enabled) + return; + + if (INTEL_GEN(i915) >= 9) + gen9_disable_rc6(i915); + else if (IS_CHERRYVIEW(i915)) + cherryview_disable_rc6(i915); + else if (IS_VALLEYVIEW(i915)) + valleyview_disable_rc6(i915); + else if (INTEL_GEN(i915) >= 6) + gen6_disable_rc6(i915); + + i915->gt_pm.rc6.enabled = false; +} + +static void intel_disable_rps(struct drm_i915_private *i915) +{ + lockdep_assert_held(&i915->gt_pm.rps.lock); + + if (!i915->gt_pm.rps.enabled) + return; + + if (INTEL_GEN(i915) >= 9) + gen9_disable_rps(i915); + else if (IS_CHERRYVIEW(i915)) + cherryview_disable_rps(i915); + else if (IS_VALLEYVIEW(i915)) + valleyview_disable_rps(i915); + else if (INTEL_GEN(i915) >= 6) + gen6_disable_rps(i915); + else if (INTEL_GEN(i915) >= 5) + ironlake_disable_drps(i915); + + i915->gt_pm.rps.enabled = false; +} + +void intel_disable_gt_powersave(struct drm_i915_private *i915) +{ + mutex_lock(&i915->gt_pm.rps.lock); + + intel_disable_rc6(i915); + intel_disable_rps(i915); + if (HAS_LLC(i915)) + intel_disable_llc_pstate(i915); + + mutex_unlock(&i915->gt_pm.rps.lock); +} + +void intel_cleanup_gt_powersave(struct drm_i915_private *i915) +{ + if (IS_VALLEYVIEW(i915)) + valleyview_cleanup_gt_powersave(i915); + + if (!HAS_RC6(i915)) + intel_runtime_pm_put(i915); +} + static int byt_gpu_freq(const struct drm_i915_private *i915, int val) { const struct intel_rps *rps = &i915->gt_pm.rps; diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h index afb7a5858dff..bd400c9aed7c 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/intel_gt_pm.h @@ -93,11 +93,12 @@ struct intel_gt_pm { void intel_gpu_ips_init(struct drm_i915_private *i915); void intel_gpu_ips_teardown(void); -void intel_init_gt_powersave(struct drm_i915_private *i915); -void intel_cleanup_gt_powersave(struct drm_i915_private *i915); void intel_sanitize_gt_powersave(struct drm_i915_private *i915); + +void intel_init_gt_powersave(struct drm_i915_private *i915); void intel_enable_gt_powersave(struct drm_i915_private *i915); void intel_disable_gt_powersave(struct drm_i915_private *i915); +void intel_cleanup_gt_powersave(struct drm_i915_private *i915); void intel_gt_pm_irq_handler(struct drm_i915_private *i915, u32 pm_iir);