diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c
index f8b75814796d..b69ddb5be3e4 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/intel_gt_pm.c
@@ -2400,6 +2400,18 @@ static void intel_init_emon(struct drm_i915_private *dev_priv)
 	dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
 }
 
+void intel_sanitize_gt_powersave(struct drm_i915_private *i915)
+{
+	i915->gt_pm.rps.enabled = true; /* force RPS disabling */
+	i915->gt_pm.rc6.enabled = true; /* force RC6 disabling */
+	intel_disable_gt_powersave(i915);
+
+	if (INTEL_GEN(i915) >= 11)
+		gen11_reset_rps_interrupts(i915);
+	else
+		gen6_reset_rps_interrupts(i915);
+}
+
 void intel_init_gt_powersave(struct drm_i915_private *i915)
 {
 	struct intel_rps *rps = &i915->gt_pm.rps;
@@ -2482,91 +2494,6 @@ void intel_init_gt_powersave(struct drm_i915_private *i915)
 	mutex_unlock(&rps->lock);
 }
 
-void intel_cleanup_gt_powersave(struct drm_i915_private *i915)
-{
-	if (IS_VALLEYVIEW(i915))
-		valleyview_cleanup_gt_powersave(i915);
-
-	if (!HAS_RC6(i915))
-		intel_runtime_pm_put(i915);
-}
-
-void intel_sanitize_gt_powersave(struct drm_i915_private *i915)
-{
-	i915->gt_pm.rps.enabled = true; /* force RPS disabling */
-	i915->gt_pm.rc6.enabled = true; /* force RC6 disabling */
-	intel_disable_gt_powersave(i915);
-
-	if (INTEL_GEN(i915) >= 11)
-		gen11_reset_rps_interrupts(i915);
-	else
-		gen6_reset_rps_interrupts(i915);
-}
-
-static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
-{
-	lockdep_assert_held(&i915->gt_pm.rps.lock);
-
-	if (!i915->gt_pm.llc_pstate.enabled)
-		return;
-
-	/* Currently there is no HW configuration to be done to disable. */
-
-	i915->gt_pm.llc_pstate.enabled = false;
-}
-
-static void intel_disable_rc6(struct drm_i915_private *i915)
-{
-	lockdep_assert_held(&i915->gt_pm.rps.lock);
-
-	if (!i915->gt_pm.rc6.enabled)
-		return;
-
-	if (INTEL_GEN(i915) >= 9)
-		gen9_disable_rc6(i915);
-	else if (IS_CHERRYVIEW(i915))
-		cherryview_disable_rc6(i915);
-	else if (IS_VALLEYVIEW(i915))
-		valleyview_disable_rc6(i915);
-	else if (INTEL_GEN(i915) >= 6)
-		gen6_disable_rc6(i915);
-
-	i915->gt_pm.rc6.enabled = false;
-}
-
-static void intel_disable_rps(struct drm_i915_private *i915)
-{
-	lockdep_assert_held(&i915->gt_pm.rps.lock);
-
-	if (!i915->gt_pm.rps.enabled)
-		return;
-
-	if (INTEL_GEN(i915) >= 9)
-		gen9_disable_rps(i915);
-	else if (IS_CHERRYVIEW(i915))
-		cherryview_disable_rps(i915);
-	else if (IS_VALLEYVIEW(i915))
-		valleyview_disable_rps(i915);
-	else if (INTEL_GEN(i915) >= 6)
-		gen6_disable_rps(i915);
-	else if (INTEL_GEN(i915) >= 5)
-		ironlake_disable_drps(i915);
-
-	i915->gt_pm.rps.enabled = false;
-}
-
-void intel_disable_gt_powersave(struct drm_i915_private *i915)
-{
-	mutex_lock(&i915->gt_pm.rps.lock);
-
-	intel_disable_rc6(i915);
-	intel_disable_rps(i915);
-	if (HAS_LLC(i915))
-		intel_disable_llc_pstate(i915);
-
-	mutex_unlock(&i915->gt_pm.rps.lock);
-}
-
 static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
 {
 	lockdep_assert_held(&i915->gt_pm.rps.lock);
@@ -2651,6 +2578,79 @@ void intel_enable_gt_powersave(struct drm_i915_private *i915)
 	mutex_unlock(&i915->gt_pm.rps.lock);
 }
 
+static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
+{
+	lockdep_assert_held(&i915->gt_pm.rps.lock);
+
+	if (!i915->gt_pm.llc_pstate.enabled)
+		return;
+
+	/* Currently there is no HW configuration to be done to disable. */
+
+	i915->gt_pm.llc_pstate.enabled = false;
+}
+
+static void intel_disable_rc6(struct drm_i915_private *i915)
+{
+	lockdep_assert_held(&i915->gt_pm.rps.lock);
+
+	if (!i915->gt_pm.rc6.enabled)
+		return;
+
+	if (INTEL_GEN(i915) >= 9)
+		gen9_disable_rc6(i915);
+	else if (IS_CHERRYVIEW(i915))
+		cherryview_disable_rc6(i915);
+	else if (IS_VALLEYVIEW(i915))
+		valleyview_disable_rc6(i915);
+	else if (INTEL_GEN(i915) >= 6)
+		gen6_disable_rc6(i915);
+
+	i915->gt_pm.rc6.enabled = false;
+}
+
+static void intel_disable_rps(struct drm_i915_private *i915)
+{
+	lockdep_assert_held(&i915->gt_pm.rps.lock);
+
+	if (!i915->gt_pm.rps.enabled)
+		return;
+
+	if (INTEL_GEN(i915) >= 9)
+		gen9_disable_rps(i915);
+	else if (IS_CHERRYVIEW(i915))
+		cherryview_disable_rps(i915);
+	else if (IS_VALLEYVIEW(i915))
+		valleyview_disable_rps(i915);
+	else if (INTEL_GEN(i915) >= 6)
+		gen6_disable_rps(i915);
+	else if (INTEL_GEN(i915) >= 5)
+		ironlake_disable_drps(i915);
+
+	i915->gt_pm.rps.enabled = false;
+}
+
+void intel_disable_gt_powersave(struct drm_i915_private *i915)
+{
+	mutex_lock(&i915->gt_pm.rps.lock);
+
+	intel_disable_rc6(i915);
+	intel_disable_rps(i915);
+	if (HAS_LLC(i915))
+		intel_disable_llc_pstate(i915);
+
+	mutex_unlock(&i915->gt_pm.rps.lock);
+}
+
+void intel_cleanup_gt_powersave(struct drm_i915_private *i915)
+{
+	if (IS_VALLEYVIEW(i915))
+		valleyview_cleanup_gt_powersave(i915);
+
+	if (!HAS_RC6(i915))
+		intel_runtime_pm_put(i915);
+}
+
 static int byt_gpu_freq(const struct drm_i915_private *i915, int val)
 {
 	const struct intel_rps *rps = &i915->gt_pm.rps;
diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h
index afb7a5858dff..bd400c9aed7c 100644
--- a/drivers/gpu/drm/i915/intel_gt_pm.h
+++ b/drivers/gpu/drm/i915/intel_gt_pm.h
@@ -93,11 +93,12 @@ struct intel_gt_pm {
 void intel_gpu_ips_init(struct drm_i915_private *i915);
 void intel_gpu_ips_teardown(void);
 
-void intel_init_gt_powersave(struct drm_i915_private *i915);
-void intel_cleanup_gt_powersave(struct drm_i915_private *i915);
 void intel_sanitize_gt_powersave(struct drm_i915_private *i915);
+
+void intel_init_gt_powersave(struct drm_i915_private *i915);
 void intel_enable_gt_powersave(struct drm_i915_private *i915);
 void intel_disable_gt_powersave(struct drm_i915_private *i915);
+void intel_cleanup_gt_powersave(struct drm_i915_private *i915);
 
 void intel_gt_pm_irq_handler(struct drm_i915_private *i915, u32 pm_iir);
 
