From patchwork Thu May 3 06:37:32 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10377213 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 50F036037D for ; Thu, 3 May 2018 06:40:16 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 409C029067 for ; Thu, 3 May 2018 06:40:16 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3E1D6290C7; Thu, 3 May 2018 06:40:16 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2D953290C4 for ; Thu, 3 May 2018 06:40:14 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F2F296E6C1; Thu, 3 May 2018 06:39:56 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 239726E6AA for ; Thu, 3 May 2018 06:39:50 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11578300-1500050 for multiple; Thu, 03 May 2018 07:39:44 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Thu, 03 May 2018 07:39:42 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 3 May 2018 07:37:32 +0100 Message-Id: <20180503063757.22238-46-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503063757.22238-1-chris@chris-wilson.co.uk> References: <20180503063757.22238-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 46/71] drm/i915: Split control of rps and rc6 X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP Allow ourselves to individually toggle rps or rc6. This will be used later when we want to enable rps/rc6 at different phases during the device bring up. Whilst here, convert the intel_$verb_gt_powersave over to intel_gt_pm_$verb scheme. v2: Resurrect llc_pstate, we will need to restore state on resume. Signed-off-by: Chris Wilson --- drivers/gpu/drm/i915/i915_drv.c | 6 +- drivers/gpu/drm/i915/i915_gem.c | 23 +++--- drivers/gpu/drm/i915/intel_display.c | 6 +- drivers/gpu/drm/i915/intel_gt_pm.c | 104 ++++++++++++++++----------- drivers/gpu/drm/i915/intel_gt_pm.h | 17 +++-- 5 files changed, 95 insertions(+), 61 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index fef245f01a32..3ed2a85ccac0 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -1067,7 +1067,7 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) */ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) { - intel_sanitize_gt_powersave(dev_priv); + intel_gt_pm_sanitize(dev_priv); intel_uncore_fini(dev_priv); i915_mmio_cleanup(dev_priv); pci_dev_put(dev_priv->bridge_dev); @@ -1176,7 +1176,7 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv) intel_uncore_sanitize(dev_priv); /* BIOS often leaves RC6 enabled, but disable it for hw init */ - intel_sanitize_gt_powersave(dev_priv); + intel_gt_pm_sanitize(dev_priv); intel_opregion_setup(dev_priv); @@ -1716,7 +1716,7 @@ static int i915_drm_resume(struct drm_device *dev) int ret; disable_rpm_wakeref_asserts(dev_priv); - intel_sanitize_gt_powersave(dev_priv); + intel_gt_pm_sanitize(dev_priv); ret = i915_ggtt_enable_hw(dev_priv); if (ret) diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 3d6e749787a8..1b47eeed7820 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -221,7 +221,10 @@ void i915_gem_unpark(struct drm_i915_private *i915) if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */ i915->gt.epoch = 1; - intel_enable_gt_powersave(i915); + intel_gt_pm_enable_rps(i915); + intel_gt_pm_enable_rc6(i915); + intel_gt_pm_enable_llc(i915); + i915_update_gfx_val(i915); if (INTEL_GEN(i915) >= 6) gen6_rps_busy(i915); @@ -5358,10 +5361,12 @@ int i915_gem_init(struct drm_i915_private *dev_priv) goto err_unlock; } + intel_gt_pm_init(dev_priv); + ret = i915_gem_contexts_init(dev_priv); if (ret) { GEM_BUG_ON(ret == -EIO); - goto err_ggtt; + goto err_pm; } ret = intel_engines_init(dev_priv); @@ -5370,11 +5375,9 @@ int i915_gem_init(struct drm_i915_private *dev_priv) goto err_context; } - intel_init_gt_powersave(dev_priv); - ret = intel_uc_init(dev_priv); if (ret) - goto err_pm; + goto err_engines; ret = i915_gem_init_hw(dev_priv); if (ret) @@ -5422,15 +5425,15 @@ int i915_gem_init(struct drm_i915_private *dev_priv) intel_uc_fini_hw(dev_priv); err_uc_init: intel_uc_fini(dev_priv); -err_pm: - if (ret != -EIO) { - intel_cleanup_gt_powersave(dev_priv); +err_engines: + if (ret != -EIO) i915_gem_cleanup_engines(dev_priv); - } err_context: if (ret != -EIO) i915_gem_contexts_fini(dev_priv); -err_ggtt: +err_pm: + if (ret != -EIO) + intel_gt_pm_fini(dev_priv); err_unlock: intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); mutex_unlock(&dev_priv->drm.struct_mutex); diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 444d09539f70..464a3c787fbd 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15549,7 +15549,9 @@ void intel_modeset_cleanup(struct drm_device *dev) flush_work(&dev_priv->atomic_helper.free_work); WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); - intel_disable_gt_powersave(dev_priv); + intel_gt_pm_disable_llc(dev_priv); + intel_gt_pm_disable_rc6(dev_priv); + intel_gt_pm_disable_rps(dev_priv); /* * Interrupts and polling as the first thing to avoid creating havoc. @@ -15578,7 +15580,7 @@ void intel_modeset_cleanup(struct drm_device *dev) intel_cleanup_overlay(dev_priv); - intel_cleanup_gt_powersave(dev_priv); + intel_gt_pm_fini(dev_priv); intel_teardown_gmbus(dev_priv); diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c index b69ddb5be3e4..53b7a669bf83 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/intel_gt_pm.c @@ -2400,11 +2400,15 @@ static void intel_init_emon(struct drm_i915_private *dev_priv) dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); } -void intel_sanitize_gt_powersave(struct drm_i915_private *i915) +void intel_gt_pm_sanitize(struct drm_i915_private *i915) { - i915->gt_pm.rps.enabled = true; /* force RPS disabling */ + intel_gt_pm_disable_llc(i915); + i915->gt_pm.rc6.enabled = true; /* force RC6 disabling */ - intel_disable_gt_powersave(i915); + intel_gt_pm_disable_rc6(i915); + + i915->gt_pm.rps.enabled = true; /* force RPS disabling */ + intel_gt_pm_disable_rps(i915); if (INTEL_GEN(i915) >= 11) gen11_reset_rps_interrupts(i915); @@ -2412,7 +2416,7 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *i915) gen6_reset_rps_interrupts(i915); } -void intel_init_gt_powersave(struct drm_i915_private *i915) +void intel_gt_pm_init(struct drm_i915_private *i915) { struct intel_rps *rps = &i915->gt_pm.rps; @@ -2494,19 +2498,7 @@ void intel_init_gt_powersave(struct drm_i915_private *i915) mutex_unlock(&rps->lock); } -static inline void intel_enable_llc_pstate(struct drm_i915_private *i915) -{ - lockdep_assert_held(&i915->gt_pm.rps.lock); - - if (i915->gt_pm.llc_pstate.enabled) - return; - - gen6_update_ring_freq(i915); - - i915->gt_pm.llc_pstate.enabled = true; -} - -static void intel_enable_rc6(struct drm_i915_private *i915) +static void __enable_rc6(struct drm_i915_private *i915) { lockdep_assert_held(&i915->gt_pm.rps.lock); @@ -2527,7 +2519,17 @@ static void intel_enable_rc6(struct drm_i915_private *i915) i915->gt_pm.rc6.enabled = true; } -static void intel_enable_rps(struct drm_i915_private *i915) +void intel_gt_pm_enable_rc6(struct drm_i915_private *i915) +{ + if (!HAS_RC6(i915)) + return; + + mutex_lock(&i915->gt_pm.rps.lock); + __enable_rc6(i915); + mutex_unlock(&i915->gt_pm.rps.lock); +} + +static void __enable_rps(struct drm_i915_private *i915) { struct intel_rps *rps = &i915->gt_pm.rps; @@ -2560,37 +2562,38 @@ static void intel_enable_rps(struct drm_i915_private *i915) rps->enabled = true; } -void intel_enable_gt_powersave(struct drm_i915_private *i915) +void intel_gt_pm_enable_rps(struct drm_i915_private *i915) { - /* Powersaving is controlled by the host when inside a VM */ - if (intel_vgpu_active(i915)) + if (!HAS_RPS(i915)) return; mutex_lock(&i915->gt_pm.rps.lock); - - if (HAS_RC6(i915)) - intel_enable_rc6(i915); - if (HAS_RPS(i915)) - intel_enable_rps(i915); - if (HAS_LLC(i915)) - intel_enable_llc_pstate(i915); - + __enable_rps(i915); mutex_unlock(&i915->gt_pm.rps.lock); } -static inline void intel_disable_llc_pstate(struct drm_i915_private *i915) +static void __enable_llc(struct drm_i915_private *i915) { lockdep_assert_held(&i915->gt_pm.rps.lock); - if (!i915->gt_pm.llc_pstate.enabled) + if (i915->gt_pm.llc_pstate.enabled) return; - /* Currently there is no HW configuration to be done to disable. */ + gen6_update_ring_freq(i915); + i915->gt_pm.llc_pstate.enabled = true; +} - i915->gt_pm.llc_pstate.enabled = false; +void intel_gt_pm_enable_llc(struct drm_i915_private *i915) +{ + if (!HAS_LLC(i915)) + return; + + mutex_lock(&i915->gt_pm.rps.lock); + __enable_llc(i915); + mutex_unlock(&i915->gt_pm.rps.lock); } -static void intel_disable_rc6(struct drm_i915_private *i915) +static void __disable_rc6(struct drm_i915_private *i915) { lockdep_assert_held(&i915->gt_pm.rps.lock); @@ -2609,7 +2612,14 @@ static void intel_disable_rc6(struct drm_i915_private *i915) i915->gt_pm.rc6.enabled = false; } -static void intel_disable_rps(struct drm_i915_private *i915) +void intel_gt_pm_disable_rc6(struct drm_i915_private *i915) +{ + mutex_lock(&i915->gt_pm.rps.lock); + __disable_rc6(i915); + mutex_unlock(&i915->gt_pm.rps.lock); +} + +static void __disable_rps(struct drm_i915_private *i915) { lockdep_assert_held(&i915->gt_pm.rps.lock); @@ -2630,19 +2640,31 @@ static void intel_disable_rps(struct drm_i915_private *i915) i915->gt_pm.rps.enabled = false; } -void intel_disable_gt_powersave(struct drm_i915_private *i915) +void intel_gt_pm_disable_rps(struct drm_i915_private *i915) { mutex_lock(&i915->gt_pm.rps.lock); + __disable_rps(i915); + mutex_unlock(&i915->gt_pm.rps.lock); +} - intel_disable_rc6(i915); - intel_disable_rps(i915); - if (HAS_LLC(i915)) - intel_disable_llc_pstate(i915); +static void __disable_llc(struct drm_i915_private *i915) +{ + lockdep_assert_held(&i915->gt_pm.rps.lock); + if (!i915->gt_pm.llc_pstate.enabled) + return; + + i915->gt_pm.llc_pstate.enabled = false; +} + +void intel_gt_pm_disable_llc(struct drm_i915_private *i915) +{ + mutex_lock(&i915->gt_pm.rps.lock); + __disable_llc(i915); mutex_unlock(&i915->gt_pm.rps.lock); } -void intel_cleanup_gt_powersave(struct drm_i915_private *i915) +void intel_gt_pm_fini(struct drm_i915_private *i915) { if (IS_VALLEYVIEW(i915)) valleyview_cleanup_gt_powersave(i915); diff --git a/drivers/gpu/drm/i915/intel_gt_pm.h b/drivers/gpu/drm/i915/intel_gt_pm.h index bd400c9aed7c..2e93bc6238c1 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.h +++ b/drivers/gpu/drm/i915/intel_gt_pm.h @@ -93,12 +93,19 @@ struct intel_gt_pm { void intel_gpu_ips_init(struct drm_i915_private *i915); void intel_gpu_ips_teardown(void); -void intel_sanitize_gt_powersave(struct drm_i915_private *i915); +void intel_gt_pm_sanitize(struct drm_i915_private *i915); -void intel_init_gt_powersave(struct drm_i915_private *i915); -void intel_enable_gt_powersave(struct drm_i915_private *i915); -void intel_disable_gt_powersave(struct drm_i915_private *i915); -void intel_cleanup_gt_powersave(struct drm_i915_private *i915); +void intel_gt_pm_init(struct drm_i915_private *i915); +void intel_gt_pm_fini(struct drm_i915_private *i915); + +void intel_gt_pm_enable_rps(struct drm_i915_private *i915); +void intel_gt_pm_disable_rps(struct drm_i915_private *i915); + +void intel_gt_pm_enable_rc6(struct drm_i915_private *i915); +void intel_gt_pm_disable_rc6(struct drm_i915_private *i915); + +void intel_gt_pm_enable_llc(struct drm_i915_private *i915); +void intel_gt_pm_disable_llc(struct drm_i915_private *i915); void intel_gt_pm_irq_handler(struct drm_i915_private *i915, u32 pm_iir);