From patchwork Thu May 3 06:37:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10377205 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 545556037D for ; Thu, 3 May 2018 06:40:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 400AB29053 for ; Thu, 3 May 2018 06:40:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 34D5728E74; Thu, 3 May 2018 06:40:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B344928E74 for ; Thu, 3 May 2018 06:40:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id F100C6E6AA; Thu, 3 May 2018 06:39:51 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 208406E69F for ; Thu, 3 May 2018 06:39:48 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11578303-1500050 for multiple; Thu, 03 May 2018 07:39:46 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Thu, 03 May 2018 07:39:45 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 3 May 2018 07:37:33 +0100 Message-Id: <20180503063757.22238-47-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503063757.22238-1-chris@chris-wilson.co.uk> References: <20180503063757.22238-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 47/71] drm/i915: Enabling rc6 and rps have different requirements, so separate them X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP On Ironlake, we are required to not enable rc6 until the GPU is loaded with a valid context; after that point it can start to use a powersaving context for rc6. This seems a reasonable requirement to impose on all generations as we are already priming the system by loading a context on resume. We can simply then delay enabling rc6 until we know the GPU is awake. v2: Reorder intel_gt_pm_fini in i915_gem_fini to match setup ordering, and remove the superfluous intel_gt_pm_sanitize() on mmio cleanup. Signed-off-by: Chris Wilson Cc: Sagar Arun Kamble --- drivers/gpu/drm/i915/i915_drv.c | 2 +- drivers/gpu/drm/i915/i915_gem.c | 40 +++++++++++++++++++++------- drivers/gpu/drm/i915/intel_display.c | 6 ----- drivers/gpu/drm/i915/intel_gt_pm.c | 2 ++ 4 files changed, 33 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c index 3ed2a85ccac0..74b99cf65adb 100644 --- a/drivers/gpu/drm/i915/i915_drv.c +++ b/drivers/gpu/drm/i915/i915_drv.c @@ -639,6 +639,7 @@ static void i915_gem_fini(struct drm_i915_private *dev_priv) intel_uc_fini(dev_priv); i915_gem_cleanup_engines(dev_priv); i915_gem_contexts_fini(dev_priv); + intel_gt_pm_fini(dev_priv); mutex_unlock(&dev_priv->drm.struct_mutex); intel_uc_fini_misc(dev_priv); @@ -1067,7 +1068,6 @@ static int i915_driver_init_mmio(struct drm_i915_private *dev_priv) */ static void i915_driver_cleanup_mmio(struct drm_i915_private *dev_priv) { - intel_gt_pm_sanitize(dev_priv); intel_uncore_fini(dev_priv); i915_mmio_cleanup(dev_priv); pci_dev_put(dev_priv->bridge_dev); diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c index 1b47eeed7820..1af135925073 100644 --- a/drivers/gpu/drm/i915/i915_gem.c +++ b/drivers/gpu/drm/i915/i915_gem.c @@ -221,10 +221,6 @@ void i915_gem_unpark(struct drm_i915_private *i915) if (unlikely(++i915->gt.epoch == 0)) /* keep 0 as invalid */ i915->gt.epoch = 1; - intel_gt_pm_enable_rps(i915); - intel_gt_pm_enable_rc6(i915); - intel_gt_pm_enable_llc(i915); - i915_update_gfx_val(i915); if (INTEL_GEN(i915) >= 6) gen6_rps_busy(i915); @@ -3341,11 +3337,38 @@ void i915_gem_set_wedged(struct drm_i915_private *i915) i915_gem_reset_finish_engine(engine); } + intel_gt_pm_sanitize(i915); + GEM_TRACE("end\n"); wake_up_all(&i915->gpu_error.reset_queue); } +static int load_power_context(struct drm_i915_private *i915) +{ + int err; + + intel_gt_pm_sanitize(i915); + intel_gt_pm_enable_rps(i915); + + err = i915_gem_switch_to_kernel_context(i915); + if (err) + goto err; + + err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED); + if (err) + goto err; + + intel_gt_pm_enable_rc6(i915); + intel_gt_pm_enable_llc(i915); + + return 0; + +err: + intel_gt_pm_sanitize(i915); + return err; +} + bool i915_gem_unset_wedged(struct drm_i915_private *i915) { struct i915_timeline *tl; @@ -5040,7 +5063,7 @@ void i915_gem_resume(struct drm_i915_private *i915) intel_uc_resume(i915); /* Always reload a context for powersaving. */ - if (i915_gem_switch_to_kernel_context(i915)) + if (load_power_context(i915)) goto err_wedged; out_unlock: @@ -5235,11 +5258,8 @@ static int __intel_engines_record_defaults(struct drm_i915_private *i915) goto err_active; } - err = i915_gem_switch_to_kernel_context(i915); - if (err) - goto err_active; - - err = i915_gem_wait_for_idle(i915, I915_WAIT_LOCKED); + /* Flush the default context image to memory, and enable powersaving. */ + err = load_power_context(i915); if (err) goto err_active; diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c index 464a3c787fbd..e7cb31ab0dd1 100644 --- a/drivers/gpu/drm/i915/intel_display.c +++ b/drivers/gpu/drm/i915/intel_display.c @@ -15549,10 +15549,6 @@ void intel_modeset_cleanup(struct drm_device *dev) flush_work(&dev_priv->atomic_helper.free_work); WARN_ON(!llist_empty(&dev_priv->atomic_helper.free_list)); - intel_gt_pm_disable_llc(dev_priv); - intel_gt_pm_disable_rc6(dev_priv); - intel_gt_pm_disable_rps(dev_priv); - /* * Interrupts and polling as the first thing to avoid creating havoc. * Too much stuff here (turning of connectors, ...) would @@ -15580,8 +15576,6 @@ void intel_modeset_cleanup(struct drm_device *dev) intel_cleanup_overlay(dev_priv); - intel_gt_pm_fini(dev_priv); - intel_teardown_gmbus(dev_priv); destroy_workqueue(dev_priv->modeset_wq); diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c index 53b7a669bf83..42171c4ba20c 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/intel_gt_pm.c @@ -2666,6 +2666,8 @@ void intel_gt_pm_disable_llc(struct drm_i915_private *i915) void intel_gt_pm_fini(struct drm_i915_private *i915) { + intel_gt_pm_sanitize(i915); + if (IS_VALLEYVIEW(i915)) valleyview_cleanup_gt_powersave(i915);