From patchwork Thu May 3 06:37:35 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chris Wilson X-Patchwork-Id: 10377215 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5D9D6603B4 for ; Thu, 3 May 2018 06:40:17 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3D25B290B6 for ; Thu, 3 May 2018 06:40:17 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 3BDDF290C7; Thu, 3 May 2018 06:40:17 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 33A66290DA for ; Thu, 3 May 2018 06:40:16 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 3B4536E6A5; Thu, 3 May 2018 06:40:02 +0000 (UTC) X-Original-To: intel-gfx@lists.freedesktop.org Delivered-To: intel-gfx@lists.freedesktop.org Received: from fireflyinternet.com (mail.fireflyinternet.com [109.228.58.192]) by gabe.freedesktop.org (Postfix) with ESMTPS id 4293A6E6D7 for ; Thu, 3 May 2018 06:40:00 +0000 (UTC) X-Default-Received-SPF: pass (skip=forwardok (res=PASS)) x-ip-name=78.156.65.138; Received: from haswell.alporthouse.com (unverified [78.156.65.138]) by fireflyinternet.com (Firefly Internet (M1)) with ESMTP id 11578306-1500050 for multiple; Thu, 03 May 2018 07:39:51 +0100 Received: by haswell.alporthouse.com (sSMTP sendmail emulation); Thu, 03 May 2018 07:39:49 +0100 From: Chris Wilson To: intel-gfx@lists.freedesktop.org Date: Thu, 3 May 2018 07:37:35 +0100 Message-Id: <20180503063757.22238-49-chris@chris-wilson.co.uk> X-Mailer: git-send-email 2.17.0 In-Reply-To: <20180503063757.22238-1-chris@chris-wilson.co.uk> References: <20180503063757.22238-1-chris@chris-wilson.co.uk> X-Originating-IP: 78.156.65.138 X-Country: code=GB country="United Kingdom" ip=78.156.65.138 Subject: [Intel-gfx] [PATCH 49/71] drm/i915: Refactor frequency bounds computation X-BeenThere: intel-gfx@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Intel graphics driver community testing & development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: intel-gfx-bounces@lists.freedesktop.org Sender: "Intel-gfx" X-Virus-Scanned: ClamAV using ClamSMTP When choosing the initial frequency in intel_gt_pm_busy() we also need to calculate the current min/max bounds. As this calculation is going to become more complex with the intersection of several different limits, refactor it to a common function. The alternative wold be to feed the initial reclocking through the RPS worker, but the latency in this case is undesirable. v2: Only apply the rps->last_adj update if the frequency was unclamped. The intention is that we don't continue to accumulate the adjustment when we hit the bounds. Signed-off-by: Chris Wilson Cc: Sagar Arun Kamble --- drivers/gpu/drm/i915/intel_gt_pm.c | 57 +++++++++++------------------- 1 file changed, 21 insertions(+), 36 deletions(-) diff --git a/drivers/gpu/drm/i915/intel_gt_pm.c b/drivers/gpu/drm/i915/intel_gt_pm.c index 8d53a392afd3..c2754a9c01de 100644 --- a/drivers/gpu/drm/i915/intel_gt_pm.c +++ b/drivers/gpu/drm/i915/intel_gt_pm.c @@ -383,15 +383,25 @@ static int __intel_set_rps(struct drm_i915_private *i915, u8 val) return 0; } -static int intel_set_rps(struct drm_i915_private *i915, u8 val) +static int adjust_rps(struct drm_i915_private *i915, int freq, int adj) { struct intel_rps *rps = &i915->gt_pm.rps; + int min, max, val; int err; lockdep_assert_held(&rps->lock); GEM_BUG_ON(!rps->active); - GEM_BUG_ON(val > rps->max_freq); - GEM_BUG_ON(val < rps->min_freq); + + min = rps->min_freq_softlimit; + max = rps->max_freq_softlimit; + if (atomic_read(&rps->num_waiters) && max < rps->boost_freq) + max = rps->boost_freq; + + GEM_BUG_ON(min < rps->min_freq); + GEM_BUG_ON(max > rps->max_freq); + GEM_BUG_ON(max < min); + + val = clamp(freq + adj, min, max); err = __intel_set_rps(i915, val); if (err) @@ -400,6 +410,7 @@ static int intel_set_rps(struct drm_i915_private *i915, u8 val) if (val != rps->cur_freq) { trace_intel_gpu_freq_change(intel_gpu_freq(i915, val)); rps->cur_freq = val; + rps->last_adj = val == freq + adj ? adj : 0; } return 0; @@ -576,8 +587,8 @@ static void intel_rps_work(struct work_struct *work) struct drm_i915_private *i915 = container_of(work, struct drm_i915_private, gt_pm.rps.work); struct intel_rps *rps = &i915->gt_pm.rps; - int freq, adj, min, max; bool client_boost; + int freq, adj; u32 pm_iir; pm_iir = xchg(&rps->pm_iir, 0) & ~rps->pm_events; @@ -590,15 +601,6 @@ static void intel_rps_work(struct work_struct *work) if (!rps->active) goto unlock; - min = rps->min_freq_softlimit; - max = rps->max_freq_softlimit; - if (client_boost && max < rps->boost_freq) - max = rps->boost_freq; - - GEM_BUG_ON(min < rps->min_freq); - GEM_BUG_ON(max > rps->max_freq); - GEM_BUG_ON(max < min); - adj = rps->last_adj; freq = rps->cur_freq; if (client_boost && freq < rps->boost_freq) { @@ -609,16 +611,13 @@ static void intel_rps_work(struct work_struct *work) adj *= 2; else /* CHV needs even encode values */ adj = IS_CHERRYVIEW(i915) ? 2 : 1; - - if (freq >= max) - adj = 0; } else if (client_boost) { adj = 0; } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) { - if (freq > max_t(int, rps->efficient_freq, min)) - freq = max_t(int, rps->efficient_freq, min); - else if (freq > min_t(int, rps->efficient_freq, min)) - freq = min_t(int, rps->efficient_freq, min); + if (freq > rps->efficient_freq) + freq = rps->efficient_freq; + else if (freq > rps->idle_freq) + freq = rps->idle_freq; adj = 0; } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) { @@ -626,23 +625,17 @@ static void intel_rps_work(struct work_struct *work) adj *= 2; else /* CHV needs even encode values */ adj = IS_CHERRYVIEW(i915) ? -2 : -1; - - if (freq <= min) - adj = 0; } else { /* unknown/external event */ adj = 0; } - if (intel_set_rps(i915, clamp_t(int, freq + adj, min, max))) { + if (adjust_rps(i915, freq, adj)) DRM_DEBUG_DRIVER("Failed to set new GPU frequency\n"); - adj = 0; - } if (pm_iir) { spin_lock_irq(&i915->irq_lock); gen6_unmask_pm_irq(i915, rps->pm_events); spin_unlock_irq(&i915->irq_lock); - rps->last_adj = adj; } unlock: @@ -666,7 +659,6 @@ void intel_gt_pm_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir) void intel_gt_pm_busy(struct drm_i915_private *dev_priv) { struct intel_rps *rps = &dev_priv->gt_pm.rps; - u8 freq; if (!HAS_RPS(dev_priv)) return; @@ -681,14 +673,7 @@ void intel_gt_pm_busy(struct drm_i915_private *dev_priv) * Use the user's desired frequency as a guide, but for better * performance, jump directly to RPe as our starting frequency. */ - freq = max(rps->cur_freq, rps->efficient_freq); - if (intel_set_rps(dev_priv, - clamp(freq, - rps->min_freq_softlimit, - rps->max_freq_softlimit))) - DRM_DEBUG_DRIVER("Failed to set busy frequency\n"); - - rps->last_adj = 0; + adjust_rps(dev_priv, max(rps->cur_freq, rps->efficient_freq), 0); if (INTEL_GEN(dev_priv) >= 6) { memset(&rps->ei, 0, sizeof(rps->ei));