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[2/5] drm/i915/gtt: Combine marking engines dirty with wmb

Message ID 20180507165222.17009-2-mika.kuoppala@linux.intel.com (mailing list archive)
State New, archived
Headers show

Commit Message

Mika Kuoppala May 7, 2018, 4:52 p.m. UTC 
It is a common pattern to mark the tlbs dirty along with flushing
the writes. Introduce gen6_ppgtt_invalidate for this.

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Matthew Auld <matthew.auld@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_gem_gtt.c | 35 +++++++++++++++++++----------------
 1 file changed, 19 insertions(+), 16 deletions(-)

Comments

Chris Wilson May 7, 2018, 7:36 p.m. UTC | #1 
Quoting Mika Kuoppala (2018-05-07 17:52:19)
> It is a common pattern to mark the tlbs dirty along with flushing
> the writes. Introduce gen6_ppgtt_invalidate for this.

It wasn't that common at all. We were careful not to do more wmb() than
required before; not so now.
-Chris
diff mbox

Patch

diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index 2963d3d71729..b162617afe18 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -108,6 +108,21 @@ 
 static int
 i915_get_ggtt_vma_pages(struct i915_vma *vma);
 
+static void gen6_ppgtt_invalidate(struct i915_address_space * const vm)
+{
+	struct i915_hw_ppgtt * const ppgtt = i915_vm_to_ppgtt(vm);
+
+	/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
+	 * the page table structures, we mark them dirty so that
+	 * context switching/execlist queuing code takes extra steps
+	 * to ensure that tlbs are flushed.
+	 */
+	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
+
+	/* Flush write combining buffer */
+	wmb();
+}
+
 static void gen6_ggtt_invalidate(struct drm_i915_private *dev_priv)
 {
 	/* Flush write combining buffer */
@@ -814,15 +829,6 @@  static int gen8_mm_switch_4lvl(struct i915_hw_ppgtt *ppgtt,
 	return gen8_write_pdp(rq, 0, px_dma(&ppgtt->pml4));
 }
 
-/* PDE TLBs are a pain to invalidate on GEN8+. When we modify
- * the page table structures, we mark them dirty so that
- * context switching/execlist queuing code takes extra steps
- * to ensure that tlbs are flushed.
- */
-static void mark_tlbs_dirty(struct i915_hw_ppgtt *ppgtt)
-{
-	ppgtt->pd_dirty_rings = INTEL_INFO(ppgtt->base.i915)->ring_mask;
-}
 
 /* Removes entries from a single page table, releasing it if it's empty.
  * Caller can use the return value to update higher-level entries.
@@ -1398,7 +1404,7 @@  static int gen8_ppgtt_alloc_pdp(struct i915_address_space *vm,
 			gen8_ppgtt_set_pdpe(vm, pdp, pd, pdpe);
 			GEM_BUG_ON(pdp->used_pdpes > i915_pdpes_per_pdp(vm));
 
-			mark_tlbs_dirty(i915_vm_to_ppgtt(vm));
+			gen6_ppgtt_invalidate(vm);
 		}
 
 		ret = gen8_ppgtt_alloc_pd(vm, pd, start, length);
@@ -1724,8 +1730,7 @@  static void gen6_write_page_range(struct i915_hw_ppgtt *ppgtt,
 	gen6_for_each_pde(pt, &ppgtt->pd, start, length, pde)
 		gen6_write_pde(ppgtt, pde, pt);
 
-	mark_tlbs_dirty(ppgtt);
-	wmb();
+	gen6_ppgtt_invalidate(&ppgtt->base);
 }
 
 static inline u32 get_pd_offset(struct i915_hw_ppgtt *ppgtt)
@@ -1939,10 +1944,8 @@  static int gen6_alloc_va_range(struct i915_address_space *vm,
 		}
 	}
 
-	if (flush) {
-		mark_tlbs_dirty(ppgtt);
-		wmb();
-	}
+	if (flush)
+		gen6_ppgtt_invalidate(vm);
 
 	return 0;